基于EDA的3-8译码器的VHDL设计(使用软件Quartus2),有仿真波形

正确的程序

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY DISPLAY_DECODER IS

PORT(A3,A2,A1,A0:IN STD_LOGIC;

Y:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));

END ENTITY DISPLAY_DECODER;

ARCHITECTURE ONE OF DISPLAY_DECODER IS

SIGNAL S: STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN

S<=A3&A2&A1&A0;

WITH S SELECT

Y<="1111110" WHEN "0000",

"0110000" WHEN "0001",

"1101101" WHEN "0010",

"1111001" WHEN "0011",

"0110011" WHEN "0100",

"1011011" WHEN "0101",

"1011111" WHEN "0110",

"1110000" WHEN "0111",

"1111111" WHEN "1000",

"1111011" WHEN "1001",

"0000000" WHEN OTHERS;

END ARCHITECTURE ONE;

3.仿真波形图