led_out:OUT STD_LOGIC_VECTOR(2 DOWNTO 0) );

END COMPONENT;

COMPONENT set_array PORT(

clear,clk_1,clk_500:IN STD_LOGIC;

arr_mode:IN STD_LOGIC_VECTOR(2 DOWNTO 0);----四种状态 row:OUT STD_LOGIC_VECTOR(7 DOWNTO 0); colg:OUT STD_LOGIC_VECTOR(7 DOWNTO 0); colr:OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );

END COMPONENT;

COMPONENT set_start PORT(

start,clk_100,mode:IN STD_LOGIC; flag:IN INTEGER RANGE 0 TO 1; start_tmp:OUT INTEGER RANGE 0 TO 1 );

END COMPONENT;