COMPONENT SHOW PORT(

clk_500:IN STD_LOGIC; clear:IN STD_LOGIC; H1:IN INTEGER RANGE 0 TO 9; H2:IN INTEGER RANGE 0 TO 9; M1,S1:IN INTEGER RANGE 0 TO 9; M2,S2:IN INTEGER RANGE 0 TO 9; CAT:OUT STD_LOGIC_VECTOR(5 DOWNTO 0); DISP:OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );

END COMPONENT;

COMPONENT set_pause PORT(

clear,pause,clk_100:IN STD_LOGIC; pause_tmp:OUT STD_LOGIC );

END COMPONENT;

COMPONENT set_mode PORT(