Power will be the key limiter to system scalability as interconnection networks take up an increasingly significant portion of system power. In this paper, we propose an architectural leakage power modeling methodology that achieves 95-98 % accuracy agains

LeakagePowerModelingandOptimizationin

InterconnectionNetworks

XuningChenandLi-ShiuanPehDept.ofElectricalEngineering,PrincetonUniversity,NJ08544{xuningc,peh}@ee.princeton.edu

ABSTRACT

Powerwillbethekeylimitertosystemscalabilityasinter-connectionnetworkstakeupanincreasinglysigni cantpor-tionofsystempower.Inthispaper,weproposeanarchitec-turalleakagepowermodelingmethodologythatachieves95-98%accuracyagainstHSPICEestimates.Whenappliedtointerconnectionnetworks,combinedwithpreviousproposeddynamicpowermodels,wegainvaluableinsightsontotalnetworkpowerconsumption.Ourmodelingshowsrouterbu erstobeaprimecandidateforleakagepoweroptimiza-tion.Wethusinvestigatethedesignspaceofpower-awarebu erpolicies,proposeasuiteofpolicies,andexploretheimpactofvariouscircuitsmechanismsonthesepolicies.Simulationsshowpower-awarebu erssavingupto96.6%oftotalbu erleakagepower.

CategoriesandSubjectDescriptors

C.2.1[Computer-CommunicationNetworks]:Networkarchitectureanddesign

GeneralTerms

Measurement,Design

Keywords

Leakagepower,interconnectionnetworks,poweroptimiza-tion

1.INTRODUCTION

Aspowerbecomesthedominantconstraintinmanycom-putersystems,researchintopower-e cientsystemshasthrived.Inmanyofthesesystems,thenetworkfabricisasigni cantconsumerofpower.Thishasresultedinresearchersmodel-ing[9]andoptimizing[8,10]thedynamicpowerconsump-tionofinterconnectionnetworks.Astechnologyscalestodeepsub-micronprocesses,leakagepowerbecomesincreas-inglysigni cantascomparedtodynamicpower.Thereis

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thusagrowingneedtocharacterizeandoptimizenetworkleakagepoweraswell.

Inthispaper,weproposeanewarchitecturalmethodologyforestimatingleakagepowerthatdistinguishestechnology-dependentfromtechnology-independentvariables,provid-ingthe exibilityofanarchitecture-levelpowermodelwherearchitecturalparameterssu ce,togetherwiththerigorousaccuracyofalow-levelmodel.Anaccuratemodelallowsarchitectstorapidlyestimateleakagepowerastheyiterateacrossalternativedesigns.Weappliedourmethodologytobothon-chipandchip-to-chipinterconnectionnetworks,andvalidatedourestimatesagainstHSPICE,obtaining95-98%accuracy.

Bycombiningourproposedleakagepowermodelwithadynamicpowermodel[9],wewereabletogatherinsightsonthetotalpowerconsumptionofnetworks,characteriz-ingthepowerbreakdownofvariousnetworkcomponentsastechnologyscales.Ourmodelingguidedustoinvestigateandproposepower-awarebu ersasaleakagepoweropti-mizationtechnique.Wethenexplorethedesignspaceofarchitecturalpoliciesforpower-awarebu ers,andproposeasuiteoftechniquesthatareabletosaveupto96.6%oftotalbu erleakagepower.

2.

ANARCHITECTURALLEAKAGEPOWERMODELINGMETHODOLOGY

Leakagecurrenthas vebasiccomponents:reversebiasedpnjunctioncurrent,sub-thresholdleakagecurrent,gatedin-duceddrainleakage,punchthroughcurrentandgatetun-nelingcurrent.Theseleakagecurrentcomponentshaveanalmostlinearrelationwithtransistorwidth.Forinstance,subthresholdcurrentIsubwhichcurrentlydominatesleakagecurrentisde nedasfollows[1]:

I1 exp( Vds

V)exp(VV gs th Vsub=I0

off)tnV(1)

t

IW

0=µ

qεsi·NDEPL

2ΦVt

2

(2)

s

Foragivencircuittypeiandinputstatesatapro-cesstechnology,subthresholdcurrentisalmostproportionaltothetransistorwidthW.Although,di erentcomponentswillhavedi erentimpactonleakagecurrentastechnologyscales,e.g.gatedinduceddraincurrentwillbecomemoreandmoresigni cant,thetotalleakagecurrentstillkeepsanalmostlinearrelationwithtransistorwidth.