HYM4V33100DTYG-75中文资料(2)

HYM4V33100DTYG Series

PIN DESCRIPTION

PIN

CK0, CK1CKE/CSBAA0 ~ A10/RAS, /CAS, /WEDQM0~DQM3DQ0 ~ DQ31VCCVSSNC

PIN NAME

Clock InputsClock EnableChip Select

SDRAM Bank AddressAddress

Row Address Strobe, Column Address Strobe, Write EnableData Input/Output MaskData Input/OutputPower Supply (3.3V)GroundNo Connection

DESCRIPTION

The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK

Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refreshEnables or disables all inputs except CK, CKE and DQMSelects bank to be activated during /RAS activitySelects bank to be read/written during /CAS activityRow Address : RA0 ~ RA10, Column Address : CA0 ~ CA7Auto-precharge flag : A10

/RAS, /CAS and /WE define the operationRefer function truth table for details

Controls output buffers in read mode and masks input data in write modeMultiplexed data input / output pin

Power supply for internal circuits and input buffersGroundNo connection