Verilog程序

{0x01,0x00},

{0x01,0x00},

{0x01,0x00},

{0xFF,0xFE},

{0x01,0x00},

{0x01,0x00},

{0x02,0x80},

{0x02,0x80},

{0x04,0x40},

{0x04,0x40},

{0x08,0x20},

{0x10,0x10},

{0x20,0x08},

{0xC0,0x06},

*/

//此时的数字取模，如是汉字要第一个汉字的第一行加上第二个汉字的第一行。以此类推

parameter line0 = 32'h00800100,

line1 = 32'h20400100,

line2 = 32'h17fe0100,

line3 = 32'h12080100,

line4 = 32'h81100100,

line5 = 32'h40a0fefe,

line6 = 32'h40400100,

line7 = 32'h11b00100,

line8 = 32'h160e0280,

line9 = 32'h21100280,

linea = 32'he1100440,

lineb = 32'h21100440,

linec = 32'h21108020,

lined = 32'h22101010,

linee = 32'h22102008,

linef = 32'h4010c006;

//显示位数

reg[4:0] char_bit;

always @ (posedge clk or negedge rst_n)

if(!rst_n) char_bit <= 1'h1f;

else if(x_pos == 10'd384) char_bit <= 5'd32; //产生vsync信号

else if(x_pos > 10'd384 && x_pos <= 10'd416) char_bit <= char_bit - 1'b1;