Verilog程序

//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// always @ (posedge clk or negedge rst_n)

if(!rst_n) vsync <= 1'b1;

else if(y_cnt == 1) vsync <= 1'b0; //产生vsync信号

else if(y_cnt == V_SyncPulse+1) vsync <= 1'b1;

wire valid; //有效显示区标志

assign valid =

(x_cnt >= (H_SyncPulse+H_BackPorch)) &&

(x_cnt < (H_SyncPulse+H_BackPorch+H_ActivePix)) &&

(y_cnt >= (V_SyncPulse+V_BackPorch)) &&

(y_cnt < (V_SyncPulse+V_BackPorch+V_ActivePix));

wire[9:0] x_pos=x_cnt-H_SyncPulse-H_BackPorch;

wire[9:0] y_pos=y_cnt-V_SyncPulse-V_BackPorch;

//字符的字模

reg[7:0] vga_rgb;

/* 济(0) 大(1)

济

{0x00,0x80}, 00800100

{0x20,0x40}, 20400100

{0x17,0xFE}, 17fe0100

{0x12,0x08}, 12080100

{0x81,0x10}, 81100100

{0x40,0xA0}, 40a0fefe

{0x40,0x40}, 40400100

{0x11,0xB0}, 11b00100

{0x16,0x0E}, 160e0280

{0x21,0x10}, 21100280

{0xE1,0x10}, e1100440

{0x21,0x10}, 21100440

{0x21,0x10}, 21108020

{0x22,0x10}, 22101010

{0x22,0x10}, 22102008

{0x04,0x10}, 4010c006

大

{0x01,0x00},

{0x01,0x00},