附录四：部分源程序

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity ad0820 is

port(d_in:in std_logic_vector(7 downto 0); clk_12M,int:in std_logic; cs,rd,wr:out std_logic;

d_out:out std_logic_vector(7 downto 0) ); end ;

architecture behav of ad0820 is

type states is (st0,st1,st2,st3,st4,st5); signal current_state,next_state:states:=st0; signal d_mid:std_logic_vector(7 downto 0); signal clk:std_logic; begin

cs<='0';rd<='0'; ch: process(clk_12M)

variable data:std_logic_vector(1 downto 0); begin

if clk_12M'event and clk_12M='1' then if data="01" then data:=(others=>'0'); clk<=not clk; else

data:=data+1; end if; end if; end process ch; reg:process(clk) begin

if (clk'event and clk='1') then current_state<=next_state; end if; end process reg;

com:process(current_state,int,clk) begin

d_out<=d_mid;