MSP430G2553寄存器资料(16)

int main(void) {

WDTCTL = WDTPW + WDTHOLD; // Stop WDT P1DIR = 0xFF; // All P1.x outputs P1OUT = 0; // All P1.x reset P2DIR = 0xFF; // All P2.x outputs P2OUT = 0; // All P2.x reset P1SEL = BIT1 + BIT2 ; // P1.1 = RXD, P1.2=TXD P1SEL2 = BIT1 + BIT2 ; // P1.1 = RXD, P1.2=TXD P3DIR = 0xFF; P3OUT = 0;

UCA0CTL1 |= UCSSEL_1; UCA0BR0 = 0x03; UCA0BR1 = 0x00; UCA0MCTL = UCBRS1 + UCBRS0; UCA0CTL1 &= ~UCSWRST; IE2 |= UCA0RXIE;

__bis_SR_register(LPM3_bits + GIE); }

例程2：

int main(void) {

WDTCTL = WDTPW + WDTHOLD; P1DIR = 0xFF; P1OUT = 0; P2DIR = 0xFF; P2OUT = 0; P1SEL = BIT1 + BIT2 ; P1SEL2= BIT1 + BIT2 ; P3DIR = 0xFF; P3OUT = 0; UCA0CTL1 |= UCSSEL_1; UCA0BR0 = 0x03; UCA0BR1 = 0x00; UCA0MCTL = UCBRS1 + UCBRS0; UCA0CTL1 &= ~UCSWRST; IE2 |= UCA0RXIE;

__bis_SR_register(LPM3_bits + GIE); }

例程3：

int main(void)

// All P3.x outputs // All P3.x reset // CLK = ACLK // 32kHz/9600 = 3.41 //

// Modulation UCBRSx = 3

// **Initialize USCI state machine**// Enable USCI_A0 RX interrupt // Enter LPM3, interrupts enabled// Stop WDT // All P1.x outputs // All P1.x reset // All P2.x outputs // All P2.x reset // P1.1 = RXD, P1.2=TXD // P1.1 = RXD, P1.2=TXD // All P3.x outputs // All P3.x reset // CLK = ACLK // 32kHz/9600 = 3.41 //

// Modulation UCBRSx = 3

// **Initialize USCI state machine**// Enable USCI_A0 RX interrupt // Enter LPM3, interrupts enabled