HD74HCT373RPEL中文资料

时间:2025-07-10

元器件交易网

HD74HCT373, HD74HCT533

Octal D-type Transparent Latches (with 3-state outputs)

Octal D-type Transparent Latches (with inverted 3-state outputs)

REJ03D0666–0200 (Previous ADE-205-555)

Rev.2.00 Mar 30, 2006

Description

When the latch enable input is high, the Q outputs of HD74HCT373 will follow the D inputs and the Q outputs of HD74HCT533 will follow the inversion of the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals present at the other inputs and the state of the storage elements.

Features

LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility High Speed Operation: tpd (Data to Q) = 14 ns typ (CL = 50 pF) High Output Current: Fanout of 15 LSTTL Loads Wide Operating Voltage: VCC = 4.5 to 5.5 V Low Input Current: 1 µA max

Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Ordering Information

Part Name

Package Type

Package Code (Previous Code) PRDP0020AC-B (DP-20NEV) PRSP0020DD-B (FP-20DAV) PRSP0020DC-A (FP-20DBV) PTSP0020JB-A (TTP-20DAV)

Package Abbreviation

Taping Abbreviation

(Quantity)

pin HD74HCT373FPEL HD74HCT373RPEL HD74HCT533RPEL

SOP-20 pin (JEITA) SOP-20 pin (JEDEC)

FP RP T

EL (2,000 pcs/reel) EL (1,000 pcs/reel) ELL (2,000 pcs/reel)

pin

Note: Please consult the sales office for the above package availability.

Function Table

HD74HCT373 HD74HCT533

D Q Q Output Control Enable G

L L X No change No change

Notes: 1. H; High level, L; Low level, X; Irrelevant, Z; High impedance

HD74HCT373RPEL中文资料.doc 将本文的Word文档下载到电脑

精彩图片

热门精选

大家正在看

× 游客快捷下载通道(下载后可以自由复制和排版)

限时特价:7 元/份 原价:20元

支付方式:

开通VIP包月会员 特价:29元/月

注:下载文档有可能“只有目录或者内容不全”等情况,请下载之前注意辨别,如果您已付费且无法下载或内容有问题,请联系我们协助你处理。
微信:fanwen365 QQ:370150219