The simplescalar tool set, version 2.0(11)

时间：2025-03-09

under Contract DABT63-95-C-0127 and ARPA order no. D346. The current support for this work comes from a variety of sources, all of to which we are indebted.

Opcode:Format:Semantics:

0x0b

BC1F offset

if (!FCC)

SET_NPC(CPC + 8 + (OFFSET << 2))else

SET_NPC(CPC + 8)

Semantics:LBU:

Opcode:Format:Semantics:

SET_GPR(RT,

READ_SIGNED_BYTE(GPR(RS)+GPR(RD)))

Load byte unsigned, displaced addressing.0x22

LBU rt,offset(rs) inc_dec

SET_GPR(RT,

READ_UNSIGNED_BYTE(GPR(RS)+OFF-SET))

BC1T:Opcode:Format:Semantics:

Branch on oating point compare true.0x0c

BC1T offset

if (FCC)

SET_NPC(CPC + 8 + (OFFSET << 2))else

SET_NPC(CPC + 8)

LBU:

Opcode:Format:Semantics:

Load byte unsigned, indexed addressing.0xc1

LBU rt,(rs+rd) inc_dec

SET_GPR(RT,

READ_UNSIGNED_BYTE(GPR(RS)+GPR(RD)))

A.2 Load/store instructions

LB:

Opcode:Format:Semantics:LB:

Opcode:Format:

Load byte signed, displaced addressing.0x20

LB rt,offset(rs) inc_dec

SET_GPR(RT, READ_SIGNED_BYTE(GPR(RS)+ OFFSET))

LH:

Opcode:Format:Semantics:LH:

Opcode:

Load half signed, displaced addressing.0x24

LH rt,offset(rs) inc_dec

SET_GPR(RT,

READ_SIGNED_HALF(GPR(RS)+OFFSET))

Load byte signed, indexed addressing.0xc0

LB rt,(rs+rd) inc_dec

Load half signed, indexed addressing.0xc2

under Contract DABT63-95-C-0127 and ARPA order no. D346. The current support for this work comes from a variety of sources, all of to which we are indebted.

Format:Semantics:LHU:

Opcode:Format:Semantics:

LHU:

Opcode:Format:Semantics:

LW:

Opcode:Format:Semantics:LW:

Opcode:Format:Semantics:DLW:

Opcode:Format:Semantics:

DLW:

Opcode:Format:Semantics:

L.S:Opcode:Format:Semantics:L.S:Opcode:Format:Semantics:L.D:Opcode:

LH rt,(rs+rd) inc_dec

Format:SET_GPR(RT,

Semantics:

READ_SIGNED_HALF(GPR(RS)+GPR(RD)))

Load half unsigned, displaced addressing.0x26

LHU rt,offset(rs) inc_dec

L.D:SET_GPR(RT,

READ_UNSIGNED_HALF(GPR(RS)+OFF-Opcode:SET))

Format:Semantics:

Load half unsigned, indexed addressing.0xc3

LHU rt,(rs+rd) inc_dec

SET_GPR(RT,

READ_UNSIGNED_HALF(GPR(RS)+GPR(RD)LWL:

))

Opcode:Format:Load word, displaced addressing.Semantics:

0x28

LW rt,offset(rs) inc_dec

SET_GPR(RT, READ_WORD(GPR(RS)+OFF-SET))

LWR:

Opcode:Load word, indexed addressing.Format:0xc4

Semantics:

LW rt,(rs+rd) inc_dec

SET_GPR(RT,

READ_WORD(GPR(RS)+GPR(RD)))

SB:

Double load word, displaced addressing.Opcode:0x29

Format:DLW rt,offset(rs) inc_dec

Semantics:SET_GPR(RT, READ_WORD(GPR(RS)+OFF-SET))

SB:

SET_GPR(RT+1,

Opcode:READ_WORD(GPR(RS)+OFFSET+4))

Format:Semantics:Double load word, indexed addressing.0xce

SH:

DLW rt,(rs+rd) inc_dec

Opcode:SET_GPR(RT,

Format:READ_WORD(GPR(RS)+GPR(RD)))Semantics:SET_GPR(RT+1,

READ_WORD(GPR(RS)+GPR(RD)+4))

SH:

Load word into oating point register le,Opcode:displaced addressing.Format:Semantics:0x2a

L.S ft,offset(rs) inc_dec

SW:

SET_FPR_L(FT, READ_WORD(GPR(RS)+OFF-SET))

Opcode:Format:Load word into oating point register le,Semantics:indexed addressing.SW:

0xc5

L.S ft,(rs+rd) inc_dec

Opcode:Format:SET_FPR_L(RT,

Semantics:READ_WORD(GPR(RS)+GPR(RD)))

Load double word into oating point registerDSW:

le, displaced addressing.Opcode:Format:0x2b

Semantics:

L.D ft,offset(rs) inc_dec

SET_FPR_L(FT, READ_WORD(GPR(RS)+OFF-SET))

SET_FPR_L(FT+1,

READ_WORD(GPR(RS)+OFFSET+4))

Load double word into oating point register le, indexed addressing.0xcf

L.D ft,(rs+rd) inc_dec

SET_FPR_L(RT,

READ_WORD(GPR(RS)+GPR(RD)))SET_FPR_L(RT+1,

READ_WORD(GPR(RS)+GPR(RD)+4))

Load word left, displaced addressing.0x2c

LWL offset(rs)

Seess.def for a detailed description of thisinstruction’s semantics. NOTE: LWL does notsupport pre-/post- inc/dec.

Load word right, displaced addressing.0x2d

LWR offset(rs)

Seess.deffor a detailed description of thisinstruction’s semantics. NOTE: LWR does notsupport pre-/post- inc/dec.Store byte, displaced addressing.0x30

SB rt,offset(rs) inc_dec

WRITE_BYTE(GPR(RT), GPR(RS)+OFFSET)

Store byte, indexed addressing.0xc6

SB rt,(rs+rd) inc_dec

WRITE_BYTE(GPR(RT), GPR(RS)+GPR(RD))

Store half, displaced addressing.0x32

SH rt,offset(rs) inc_dec

WRITE_HALF(GPR(RT), GPR(RS)+OFFSET)

Store half, indexed addressing.0xc7

SH rt,(rs+rd) inc_dec

WRITE_HALF(GPR(RT), GPR(RS)+GPR(RD))

Store word, displaced addressing.0x34