sw6 : in std_logic; sw7 : in std_logic; clk : in std_logic; --系统时钟输入 hsync : out std_logic;--输出行同步、列同步以及R.G.B信号 vsync : out std_logic; rdata : out std_logic; gdata : out std_logic; bdata : out std_logic; lrdata : out std_logic; lgdata : out std_logic; lbdata : out std_logic ); end vgacode;

architecture behave of vgacode is -- horizontal timing signals constant h_data: integer:=640; --VGA时序中几个关键数据 constant h_front: integer:=16; constant h_back: integer:=48; constant h_sync: integer:=96; constant h_period: integer:= h_sync + h_data + h_front + h_back; --800 -- vertical timing signals constant v_data: integer:=480; constant v_front: integer:=10; constant v_back: integer:=33; constant v_sync: integer:=2; constant v_period: integer:= v_sync + v_data + v_front + v_back; --525 signal henable, venable : std_logic; signal clk25M : std_logic; signal hcnt: std_logic_vector(9 downto 0); -- horizontal pixel counter signal vcnt: std_logic_vector(9 downto 0); -- vertical line counter begin

process(clk) begin if clk'event and clk = '1' then --由系统时钟分频得到25MHZ的频率信号 clk25M <= not clk25M; end if; end process;

process(clk25M) ---行扫描 begin if (clk25M'event and clk25M = '1') then