Chapter 2 SOC DESIGN FLOW《SoC设计方法与实现(第2版)》郭炜等著qliu_tju_2014 qliu_tju_2013 1

Last time What is SoC

Advantages of SoC SoC Design Trend & Challenges 

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Outlines 2.1 SoC Hardware/Software co‐design flow 2.2 SoC design process 2.3 SoC verification and test

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2.1 SoC HW/SW co‐design flow2.1.1 Duality of Software and Hardware The hardware and software in an SoC system work  together to solve a problem  Why do we need both hardware and software? How do we assign tasks to hardware and software? You need to know the advantages and disadvantages of hardware and software.qliu_tju_2014 4

Hardware Pro and Con Hardware solution: PRO– Can be factors of 10X, 100X or greater speed increase– Requires less processor complexity

Hardware solution: CON– Large NRE charges – Potentially long development cycle – Little or no margin for error Only 50% of ASIC ICs work the first time– Hardware design tools can be very costly

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Software Pro and Con Software solution: PRO– No additional impact on materials costs, power  requirements, circuit complexity– Bugs are easily dealt with, even in the field!– Software design tools are relatively inexpensive– Not sensitive to sales volumes

Software solutions: CON– Relative performance vs hardware is generally far inferior– Additional algorithmic requirements forces more  processing power Bigger, faster, processors More memory Bigger power supplyqliu_tju_2014 6

2.1.2 SoC ESL Co‐design Flow

Electronic System Level design HW/SW Partitioning System modelingVirtual hardware platform for co-estimation and coverification 7

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Electronic system level (ESL) design Was first defined by Gartner Dataquest, a EDA‐industry‐ analysis firm, in 2001. Model the behavior of the entire system using a high‐level  language such as C, C++, LabVIEW, or MATLAB or using  graphical "model‐based" design tools like Simulink.

"the utilization of appropriate abstractions in order to increase comprehension about a system, and to enhance the probability of a successful implementation of functionality in a cost-effective manner."qliu_tju_2014 8

Advantages of ESL Make co‐design easier– HW/SW partitioning– Fast design space exploration– Co‐specification, co‐analysis, co‐simulation, co‐ verification– Interface synthesis– Verification of complete system – both HW/SW

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Example: HW/SW partitioningTask graph

Nodes: tasks (x,y): x is the cost when the task executes in software y is the cost when the task executes in hardware— z—: communication cost

between tasksqliu_tju_2014 10

Example: HW/SW partitioning (cont.) Optimization problem

indicates that task i is assigned to software (hardware) hi is the hardware cost of task i si is the software cost of task I C is the communication cost R is a constraintqliu_tju_2014 11

System modeling: Transaction‐level  modeling (TLM) Goals of TLM– Higher level of abstraction– More comprehensible high‐level system models– Greater simulation speeds

Communication among modules occurs at the  functional level– Each transaction is a coherent unit of interaction– Data structures and object references are passed instead  of bit vectors

Advantages of TLM– Natural way to think about high‐level communications– Object Independence– Abstraction Independenceqliu_tju_2014 12

TLM vs RTL

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Outlines 2.1 SoC (HW/SW) co‐design flow 2.2 SoC design process– 2.2.1 Design processes– 2.2.2 Design flow– 2.2.3 Design process on a platform

2.3 SoC verification and testqliu_tju_2014 14

2.2 SoC design process A generic form of an SoC design These chips have: – one (several)  processors– large amounts of  memory – bus‐based  architectures – peripherals – coprocessors– and I/O channels qliu_tju_2014

2.2.1 Design process The first part of the design process consists of  recursively developing, verifying, and refining a set of  specifications until they are detailed enough to allow  RTL coding to begin. The specifications must completely describe all the 

interfaces between the design and its environment,  including: Hardware – Functionality; External interfaces to other hardware 

(pins, buses, and how to use them); Interface to SW (register  definitions); Timing; Performance; Physical design issues such as  area and power Software – Functionality; Timing; Performance; Interface to HW SW structure, kernel qliu_tju_2014