6. 9

74LS00: Maximum delay: tpLH=tpHL=15 ns tp = 3tpLH + 3tpHL = 3×15 + 3×15 = 90 ns

6.20 (a)

F X ,Y , Z (2, 4, 7)

6.20 (b)

F A,B,C (3,4,5,6,7)

A,B,C (0,1, 2)

6.20 (b)

F A,B,C (3,4,5,6,7)

A,B,C (0,1, 2)A C B F

(c)

F A, B ,C , D (0, 2,10,12)VCC D C B A F

(d)

F W , X ,Y , Z (2,3, 4,5,8,10,12,14)VCC

W

Z Y X

FZ Y X

(e)

F W , X ,Y (0, 2, 4,5) G W , X ,Y (1, 2,3,6)VCC FY X W

G

(f)

F A, B ,C (2, 6) G C , D , E (0, 2,3)

C B A C

F

E D

G

6.21

Both halves of the ’139 are enabled simultaneously when EN_L is asserted. Therefore, two three-state drivers will be enabled to drive SDATA at the same time. Perhaps the designer forgot to put an extra inverter on the signal going to 1G or 2G, which would ensure that exactly one source drives SDATA at all times.

6.38 十进制译码器的设计 输入：四位 D、C、B、A,BCD码 输出：十位 Y0~Y9,十中取一码DCBA0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 … … 1 0 0 1

Y01 0 0 0 … … 0

Y10 1 0 0

Y20 0 1 0

Y30 0 0 1

Y40 0 0 0

Y50 0 0 0

Y60 0 0 0

Y70 0 0 0

Y80 0 0 0

Y90 0 0 0

0

0

0

0

0

0

0

0

1

1 0 1 0… …

dd d

dd d

dd d

dd d

dd d

dd d

dd d

dd d

dd d

dd d

1 1 1 1

Y0,Y1需要4个输入,Y2-Y7需要3个输入,Y8-Y9需要2个输入 2个4输入的与门，6个3输入的与门，2个2输入的与门

4-16译码器的设计,去除其中的6个输出DCBA 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 … … 1 0 0 1 1 0 1 0 … … Y0 1 0 0 0 … … 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Y1 0 1 0 0 Y2 0 0 1 0 Y3 0 0 0 1 Y4 0 0 0 0 Y5 0 0 0 0 Y6 0 0 0 0 Y7 0 0 0 0 Y8 0 0 0 0 Y9 0 0 0 0

1 1 1 1

Y 4 D C B' A DC

BA

00 01 11 10

Y 0 D C B' A Y1 D C B' A Y 3 D C B A Y 2 D C B A

00 0 01 11 10

4

8

Y 8 D C B A Y 9 D C B A

1 53 7 2 6

9

Y 5 D C B A Y 6 D C B A Y 7 D C B A

10个4输入的与门

6.41 专用译码器的设计 输入：A2、A1、A0,使能信号CS_L 输出：8个信号

BILL _ L ( A2 A1 A0 A2 A1 A0)

=(Y + Y )

' 0

' ' 1