IS61LV10248中文资料(8)

元器件交易网

IS61LV10248

ISSI

-8

-10

Max.—————————3.5—

Min.10880081060—2

Max.—————————5—

Unitnsnsnsnsnsnsnsnsnsnsns

Min.86.56.5006.5850—2

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WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)

Symbol

ParameterWrite Cycle TimeCE to Write EndAddress Setup Timeto Write End

Address Hold from Write EndAddress Setup TimeWE Pulse Width

WE Pulse Width (OE = LOW)Data Setup to Write EndData Hold from Write EndWE LOW to High-Z OutputWE HIGH to Low-Z Output

tWCtSCEtAWtHAtSAtPWE1tPWE2tSDtHDtHZWE(2)tLZWE(2)

Notes:

1.Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0Vand output loading specified in Figure 1.

2.Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

3.The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or fallingedge of the signal that terminates the write.

8Integrated Silicon Solution, Inc. — — 1-800-379-4774

Rev.C04/13/06