XQ4013EX-3BG191M中文资料

元器件交易网http://www.77cn.com.cn

QPRO XQ4000E/EX

QML High-Reliability FPGAs

DS021 (v2.2) June 25, 2000Product Specification

Product Features

Certified to MIL-PRF-38535, appendix A QML (Qualified Manufacturers Listing)

Also available under the following Standard MicrocircuitDrawings (SMD)-XC4005E5962-97522-XC4010E5962-97523-XC4013E5962-97524-XC4025E5962-97525-XC4028EX5962-98509

For more information contact the Defense Supply Center Columbus (DSCC)

System featured Field-Programmable Gate Arrays -Select-RAMTM memory: on-chip ultra-fast RAM with

·Synchronous write option ·Dual-port RAM option -Abundant flip-flops

-Flexible function generators

-Dedicated high-speed carry logic -Wide edge decoders on each edge -Hierarchy of interconnect lines -Internal 3-state bus capability

-Eight global low-skew clock or signal distribution

networks

System Performance beyond 60 MHzFlexible Array Architecture

Low Power Segmented Routing ArchitectureSystems-Oriented Features

-IEEE 1149.1-compatible boundary scan logic

support

-Individually programmable output slew rate

-Programmable input pull-up or pull-down resistors -12mA sink current per XQ4000E/EX output

Configured by Loading Binary File -Unlimited reprogrammabilityReadback Capability -Program verification

-Internal node observability

Backward Compatible with XC4000 Devices

Development System runs on most common computer platforms

-Interfaces to popular design environments

-Fully automatic mapping, placement and routing -Interactive design editor for design optimization Available Speed Grades:-XQ4000E-3 for plastic packages only--4 for ceramic packages only

-XQ4028EX -4 for all packages

More Information

For more information refer to Xilinx XC4000E and XC4000Xseries Field Programmable Gate Arrays product specifica-tion. This data sheet contains pinout tables for XQ4010Eonly. Refer to Xilinx web site for pinout tables for otherdevices. (Pinouts for XQ4000E/EX are identical toXC4000E/EX.)

()

© 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.77cn.com.cn/legal.htm.

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS021 (v2.2) June 25, 2000Product Specification1-800-255-7778

1

元器件交易网http://www.77cn.com.cn

Table 1: XQ4000E/EX Field Programmable Gate Arrays

Notes:

1.Max values of Typical Gate Range include 20-30% of CLBs used as RAM.

XQ4000E Switching Characteristics

XQ4000E Absolute Maximum Ratings(1)

Notes:

1.Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

2.Maximum DC excursion above VCC or below Ground must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During

transitions, the device pins may undershoot to –2.0V or overshoot to VCC + 2.0V, provided this over or undershoot lasts less than 10ns and with the forcing current being limited to 200 mA.

2

1-800-255-7778DS021 (v2.2) June 25, 2000

Product Specification

元器件交易网http://www.77cn.com.cn

XQ4000E Recommended Operating Conditions(1,2)

Notes:

1.With 50% of the outputs simultaneously sinking 12 mA, up to a maximum of 64 pins.

2.With no output current loads, no active input or Longline pull-up resistors, all package pins at VCC or GND, and the FPGA configured

with the development system Tie option.3.Characterized Only.

DS021 (v2.2) June 25, 2000Product Specification1-800-255-7778

3

元器件交易网http://www.77cn.com.cn

XQ4000E Switching Characteristic Guidelines

Testing of the switching parameters is modeled after testingmethods specified by MIL-M-38510/605. All devices are100% functionally tested. Internal timing parameters arederived from measuring internal test patterns. Listed beloware representative values where one global clock inputdrives one vertical clock line in each accessible column, andwhere all accessible IOB and CLB flip-flops are clocked bythe global clock net.

When fewer vertical clock lines are connected, the clock dis-tribution is faster; when multiple clock lines per column aredriven from the same global clock, the delay is longer. Formore specific, more precise, and worst-case guaranteed

data, reflecting the actual routing structure, use the valuesprovided by the static timing analyzer (TRCE in the XilinxDevelopment System) and back-annotated to the simulationnetlist. These path delays, provided as a guideline, havebeen extracted from the static timing analyzer report. Alltiming parameters assume worst-case operating conditions(supply voltage and junction temperature).

Note: -3 Speed Grade only applies to XQ4010E and XQ4013E Plastic Package options only. -4 Speed Grade applies to all XQ devices and is only available in Ceramic Packages only.

XQ4000E Global Buffer Switching Characteristics

Notes:

1.For plastic package options only.2.For ceramic package options only.

4

1-800-255-7778DS021 (v2.2) June 25, 2000

Product Specification

元器件交易网http://www.77cn.com.cn

XQ4000E Horizontal Longline Switching Characteristic Guidelines

Testing of switching parameters is modeled after testingmethods specified by MIL-M-38510/605. All devices a …… 此处隐藏：13616字，全部文档内容请下载后查看。喜欢就下载吧 ……