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M28W160CTM28W160CB

16 Mbit (1Mb x16, Boot Block)

3V Supply Flash Memory

FEATURES SUMMARY■SUPPLY VOLTAGE

–VDD = 2.7V to 3.6V Core Power Supply–VDDQ= 1.65V to 3.6V for Input/Output–VPP = 12V for fast Program (optional)

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ACCESS TIME: 70, 85, 90,100nsPROGRAMMING TIME:–10µs typical

–Double Word Programming Option

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COMMON FLASH INTERFACE–64 bit Security CodeMEMORY BLOCKS

–Parameter Blocks (Top or Bottom location)–Main Blocks

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BLOCK LOCKING

–All blocks locked at Power Up

–Any combination of blocks can be locked–■

SECURITY

–64 bit user Programmable OTP cells–64 bit unique device identifier

–One Parameter Block Permanently Lockable

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ELECTRONIC SIGNATURE–Manufacturer Code: 20h

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AUTOMATIC STAND-BY MODEPROGRAM and ERASE SUSPEND100,000 PROGRAM/ERASE CYCLES per BLOCK

ECOPACK® PACKAGES AVAILABLE

Table 1. Device Codes

Root Part Number

Device Code

M28W160CTM28W160CB

88CEh88CFh

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January 20061/50

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M28W160CT, M28W160CB

TABLE OF CONTENTS

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Figure 3. TSOP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Figure 4. TFBGA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Figure 5. Block Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8Figure 6. Security Block and Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . .8SIGNAL DESCRIPTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Address Inputs (A0-A19). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Reset (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9VDD Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9VDDQ Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9VPP Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Read.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Write.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Automatic Standby.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Read Electronic Signature Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Table 3. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Read Memory Array Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Read Electronic Signature Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Double Word Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Clear Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Protection Register Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Block Lock-Down Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

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Table 4. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14Table 5. Read Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14Table 6. Read Block Lock Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15Table 7. Read Protection Register and Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15Table 8. Program, Erase Times and Program/Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . .15BLOCK LOCKING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Reading a Block’s Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Locked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Unlocked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Lock-Down State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Locking Operations During Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Table 9. Block Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17Table 10. Protection Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17STATUS REGISTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18Erase Status (Bit 5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18Program Status (Bit 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18VPP Status (Bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18Block Protection Status (Bit 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19Reserved (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19Table 11. Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Table 12. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Table 13. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21Figure 7. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21Figure 8. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21Table 14. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21Table 15. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Figure 9. Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23Table 16. Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23Figure 10. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24Table 17. Write AC Characteristics, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . .25Figure 11. Write AC Waveforms, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26Table 18. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27Figure 12. Power-Up and Reset AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28Table 19. Power-Up and Reset AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

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PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Figure 13. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline . . . . . . . .29Table 20. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data .29Figure 14. TFBGA46 6.39x6.37mm - 8x6 ball array, 0.75mm pitch, Bottom View Package Outline30Table 21. TFBGA46 6.39x6.37mm - 8x6 ball array, 0.75mm pitch, Package Mechanical Data . . .30Figure 15. TFBGA46 Daisy Chain - Package Connections (Top view through package). . . . . . . .31Figure 16. TFBGA46 Daisy Chain - PCB Connections proposal (Top view through package). . . .31PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Table 22. Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32Table 23. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33APPENDIX A. BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Table 24. Top Boot Block Addresses, M28W160CT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34Table 25. Bottom Boot Block Addresses, M28W160CB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34APPENDIX B. COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Table 26. Query Structure Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35Table 27. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35Table 28. CFI Query System Interface Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36Table 29. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37Table 30. Primary Algorithm-Specific Extended Query Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . .38Table 31. Security Code Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39APPENDIX C. FLOWCHARTS AND PSEUDO CODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Figure 17. Program Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40Figure 18. Double Word Program Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . . . .41Figure 19. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . .42Figure 20. Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43Figure 21. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . .44Figure 22. Locking Operations Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45Figure 23. Protection Register Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . .46APPENDIX D. COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE . . . . . . .47

Table 32. Write State Machine Current/Next, sheet 1 of 2.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47Table 33. Write State Machine Current/Next, sheet 2 of 2.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Table 34. Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

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SUMMARY DESCRIPTION

The M28W160C is a 16 Mbit (1 Mbit x 16) non-vol-atile Flash memory that can be erased electricallyat the block level and programmed in-system on aWord-by-Word basis. These operations can beperformed using a single low voltage (2.7 to 3.6V)supply. VDDQ allows to drive the I/O pin down to1.65V. An optional 12V VPP power supply is pro-vided to speed up customer programming.

The device features an asymmetrical blocked ar-chitecture. The M28W160C has an array of 39blocks: 8 Parameter Blocks of 4 KWord and 31Main Blocks of 32 KWord. M28W160CT has theParameter Blocks at the top of the memory ad-dress space while the M28W160CB locates theParameter Blocks starting from the bottom. Thememory maps are shown in Figure 5, Block Ad-dresses.

The M28W160C features an instant, individualblock locking scheme that allows any block to belocked or unlocked with no latency, enabling in-stant code and data protection. All blocks havethree levels of protection. They can be locked andlocked-down individually preventing any acciden-tal programming or erasure. There is an additionalhardware protection against program and erase.When VPP ≤ VPPLK all blocks are protected againstprogram or erase. All blocks are locked at power-up.

Each block can be erased separately. Erase canbe suspended in order to perform either read orprogram in any other block and then resumed.Program can be suspended to read data in anyother block and then resumed. Each block can beprogrammed and erased over 100,000 cycles.

The device includes a 128 bit Protection Registerand a Security Block to increase the protection ofa system design. The Protection Register is divid-ed into two 64 bit segments, the first one containsa unique device number written by ST, while thesecond one is one-time-programmable by the us-er. The user programmable segment can be per-manently protected. The Security Block,parameter block 0, can be permanently protectedby the user. Figure 6, shows the Security Blockand Protection Register Memory Map.

Program and Erase commands are written to theCommand Interface of the memory. An on-chipProgram/Erase Controller takes care of the tim-ings necessary for program and erase operations.The end of a program or erase operation can bedetected and any error conditions identified. Thecommand set required to control the memory isconsistent with JEDEC standards.

The memory is offered in TSOP48 (10 X 20mm)and TFBGA46 (6.39 x 6.37mm, 0.75mm pitch)packages and is supplied with all the bits erased(set to ’1’).

In order to meet environmental requirements, SToffers the M28W160C in ECOPACK® packages.ECOPACK packages are Lead-free. The categoryof second Level Interconnect is marked on thepackage and on the inner box label, in compliancewith JEDEC Standard JESD97. The maximum rat-ings related to soldering conditions are alsomarked on the inner box label.

ECOPACK is an ST trademark. ECOPACK speci-fications are available at: http://www.77cn.com.cn.

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Table 2. Signal Names

A0-A19DQ0-DQ15VDDVDDQVPP

Address InputsData Input/Output Chip EnableOutput EnableWrite EnableResetWrite ProtectCore Power Supply

Power Supply for Input/Output Optional Supply Voltage for Fast Program & EraseGround

Not Connected Internally

VSSNC

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SIGNAL DESCRIPTIONS

See Figure 2 Logic Diagram and Table 2,SignalNames, for a brief overview of the signals connect-ed to this device.

Address Inputs (A0-A19). The Address Inputsselect the cells in the memory array to access dur-ing Bus Read operations. During Bus Write opera-tions they control the commands sent to theCommand Interface of the internal state machine.Data Input/Output (DQ0-DQ15). The Data I/Ooutputs the data stored at the selected addressduring a Bus Read operation or inputs a commandor the data to be programmed during a Write Busoperation.

The Chip Enable input acti-vates the memory control logic, input buffers, de-coders and sense amplifiers. When Chip Enable isat VILand Reset is at VIH the device is in activemode. When Chip Enable is at VIH the memory isdeselected, the outputs are high impedance andthe power consumption is reduced to the stand-bylevel.

The Output Enable controlsdata outputs during the Bus Read operation of thememory.

The Write Enable controls theBus Write operation of the memory’s CommandInterface. The data and address inputs are latchedon the rising edge of Chip Enable, E, or Write En-Write Protect is an inputthat gives an additional hardware protection foreach block. When Write Protect is at VIL, the Lock-Down is enabled and the protection status of theblock cannot be changed. When Write Protect is atVIH, the Lock-Down is disabled and the block canbe locked or unlocked. (refer to Table 7, Read Pro-tection Register and Protection Register Lock).The Reset input provides a hard-ware reset of the memory. When Reset is at VIL,the memory is in reset mode: the outputs are highimpedance and the current consumption is mini-mized. After Reset all blocks are in the Locked

state. When Reset is at VIH, the device is in normaloperation. Exiting reset mode the device entersread array mode, but a negative transition of ChipEnable or a change of the address is required toensure valid data outputs.

VDD Supply Voltage.VDD provides the powersupply to the internal core of the memory device.It is the main power supply for all operations(Read, Program and Erase).

VDDQ Supply Voltage.VDDQ provides thepower supply to the I/O pins and enables all Out-puts to be powered independently from VDD. VDDQcan be tied to VDD or can use a separate supply.VPP Program Supply Voltage.VPP is both acontrol input and a power supply pin. The twofunctions are selected by the voltage range ap-plied to the pin. The Supply Voltage VDD and theProgram Supply Voltage VPP can be applied inany order.

If VPP is kept in a low voltage range (0V to 3.6V)VPP is seen as a control input. In this case a volt-age lower than VPPLK gives an absolute protectionagainst program or erase, while VPP > VPP1 en-ables these functions (see Table 15, DC Charac-teristics for the relevant values). VPP is onlysampled at the beginning of a program or erase; achange in its value after the operation has starteddoes not have any effect and program or erase op-erations continue.

If VPP is in the range 11.4V to 12.6V it acts as apower supply pin. In this condition VPP must bestable until the Program/Erase algorithm is com-pleted (see Table 17 and 18).

VSS Ground. VSS is the reference for all voltagemeasurements.

Note: Each device in a system should haveVDD, VDDQ and VPP decoupled with a 0.1µF ca-pacitor close to the pin. See Figure 8, AC Mea-surement Load Circuit. The PCB trace widthsshould be sufficient to carry the required VPPprogram and erase currents.

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BUS OPERATIONS

There are six standard bus operations that controlthe device. These are Bus Read, Bus Write, Out-put Disable, Standby, Automatic Standby and Re-set. See Table 3, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enableor Write Enable are ignored by the memory and donot affect bus operations.

Read. Read Bus operations are used to outputthe contents of the Memory Array, the ElectronicSignature, the Status Register and the CommonFlash Interface. Both Chip Enable and Output En-able must be at VIL in order to perform a read op-eration. The Chip Enable input should be used toenable the device. Output Enable should be usedto gate data onto the output. The data read de-pends on the previous command written to thememory (see Command Interface section). SeeFigure 9, Read Mode AC Waveforms, and Table16, Read AC Characteristics, for details of whenthe output becomes valid.

Read mode is the default state of the device whenexiting Reset or after power-up.

Write.Bus Write operations write Commands tothe memory or latch Input Data to be programmed.A write operation is initiated when Chip Enableand Write Enable are at VIL with Output Enable atVIH. Commands, Input Data and Addresses arelatched on the rising edge of Write Enable or ChipEnable, whichever occurs first.

See Figures 10 and 11, Write AC Waveforms, andTables 17 and 18, Write AC Characteristics, fordetails of the timing requirements.

Output Disable. The data outputs are high im-pedance when the Output Enable is at VIH.

Standby. Standby disables most of the internalcircuitry allowing a substantial reduction of the cur-rent consumption. The memory is in stand-bywhen Chip Enable is at VIH and the device is inread mode. The power consumption is reduced tothe stand-by level and the outputs are set to highimpedance, independently from the Output Enableor Write Enable inputs. If Chip Enable switches toVIH during a program or erase operation, the de-vice enters Standby mode when finished.

Automatic Standby.Automatic Standby pro-vides a low power consumption state during Readmode. Following a read operation, the device en-ters Automatic Standby after 150ns of bus inactiv-ity even if Chip Enable is Low, VIL, and the supplycurrent is reduced to IDD1. The data Inputs/Out-puts will still output data if a bus Read operation isin progress.

Reset. During Reset mode when Output Enableis Low, VIL, the memory is deselected and the out-puts are high impedance. The memory is in Resetmode when Reset is at VIL. The power consump-tion is reduced to the Standby level, independentlyfrom the Chip Enable, Output Enable or Write En-able inputs. If Reset is pulled to VSS during a Pro-gram or Erase, this operation is aborted and thememory content is no longer valid.

Table 3. Bus Operations

OperationBus ReadBus Write Output DisableStandbyReset

VILVILVILVIHX

VILVIHVIHXX

VIHVILVIHXX

VIHVIHVIHVIHVIL

XXXXX

VPPDon't CareVDD or VPPHDon't CareDon't CareDon't Care

DQ0-DQ15Data OutputData InputHi-ZHi-ZHi-Z

Note:X = VIL or VIH, VPPH = 12V ± 5%.

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COMMAND INTERFACE

All Bus Write operations to the memory are inter-preted by the Command Interface. Commandsconsist of one or more sequential Bus Write oper-ations. An internal Program/Erase Controller han-dles all timings and verifies the correct executionof the Program and Erase commands. The Pro-gram/Erase Controller provides a Status Registerwhose output may be read at any time during, tomonitor the progress of the operation, or the Pro-gram/Erase states. See Appendix 21, Table 32,Write State Machine Current/Next, for a summaryof the Command Interface.

The Command Interface is reset to Read modewhen power is first applied, when exiting from Re-set or whenever VDD is lower than VLKO. Com-mand sequences must be followed exactly. Anyinvalid combination of commands will reset the de-vice to Read mode. Refer to Table 4, Commands,in conjunction with the text descriptions below.Read Memory Array Command

The Read command returns the memory to itsRead mode. One Bus Write cycle is required to is-sue the Read Memory Array command and returnthe memory to Read mode. Subsequent read op-erations will read the addressed location and out-put the data. When a device Reset occurs, thememory defaults to Read mode. Read Status Register Command

The Status Register indicates when a program orerase operation is complete and the success orfailure of the operation itself. Issue a Read StatusRegister command to read the Status Register’scontents. Subsequent Bus Read operations readthe Status Register at any address, until anothercommand is issued. See Table 11, Status RegisterBits, for details on the definitions of the bits.

The Read Status Register command may be is-sued at any time, even during a Program/Eraseoperation. Any Read attempt during a Program/Erase operation will automatically output the con-tent of the Status Register.

Read Electronic Signature Command

The Read Electronic Signature command readsthe Manufacturer and Device Codes and the BlockLocking Status, or the Protection Register.

The Read Electronic Signature command consistsof one write cycle, a subsequent read will outputthe Manufacturer Code, the Device Code, theBlock Lock and Lock-Down Status, or the Protec-tion and Lock Register. See Tables 5, 6 and 7 forthe valid address.

Read CFI Query Command

The Read Query Command is used to read datafrom the Common Flash Interface (CFI) MemoryArea, allowing programming equipment or appli-

cations to automatically match their interface tothe characteristics of the device. One Bus Writecycle is required to issue the Read Query Com-mand. Once the command is issued subsequentBus Read operations read from the CommonFlash Interface Memory Area. See Appendix B,Common Flash Interface, Tables 26, 27, 28, 29,30 and 31 for details on the information containedin the Common Flash Interface memory area.Block Erase Command

The Block Erase command can be used to erasea block. It sets all the bits within the selected blockto ’1’. All previous data in the block is lost. If theblock is protected then the Erase operation willabort, the data in the block will not be changed andthe Status Register will output the error.

Two Bus Write cycles are required to issue thecommand.

■The first bus cycle sets up the Erase command. ■The second latches the block address in the internal state machine and starts the Program/Erase Controller.

If the second bus cycle is not Write Erase Confirm(D0h), Status Register bits b4 and b5 are set andthe command aborts.

Erase aborts if Reset turns to VIL. As data integritycannot be guaranteed when the Erase operation isaborted, the block must be erased again.

During Erase operations the memory will acceptthe Read Status Register command and the Pro-gram/Erase Suspend command, all other com-mands will be ignored. Typical Erase times aregiven in Table 8, Program, Erase Times and Pro-gram/Erase Endurance Cycles.

See Appendix C, Figure 20, Erase Flowchart andPseudo Code, for a suggested flowchart for usingthe Erase command.Program Command

The memory array can be programmed word-by-word. Two bus write cycles are required to issuethe Program Command.

■The first bus cycle sets up the Program command.

■The second latches the Address and the Data to be written and starts the Program/Erase Controller.

During Program operations the memory will ac-cept the Read Status Register command and theProgram/Erase Suspend command. Typical Pro-gram times are given in Table 8, Program, EraseTimes and Program/Erase Endurance Cycles.Programming aborts if Reset goes to VIL. As dataintegrity cannot be guaranteed when the programoperation is aborted, the block containing the

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memory location must be erased and repro-grammed.

See Appendix C, Figure 17, Program Flowchartand Pseudo Code, for the flowchart for using theProgram command.

Double Word Program Command

This feature is offered to improve the programmingthroughput, writing a page of two adjacent wordsin parallel.The two words must differ only for theaddress A0. Programming should not be attempt-ed when VPP is not at VPPH. The command can beexecuted if VPP is below VPPH but the result is notguaranteed.

Three bus write cycles are necessary to issue theDouble Word Program command.

■The first bus cycle sets up the Double Word Program Command.

■The second bus cycle latches the Address and the Data of the first word to be written.

■The third bus cycle latches the Address and the Data of the second word to be written and starts the Program/Erase Controller.

Read operations output the Status Register con-tent after the programming has started. Program-ming aborts if Reset goes to VIL. As data integritycannot be guaranteed when the program opera-tion is aborted, the block containing the memorylocation must be erased and reprogrammed.

See Appendix C, Figure 18, Double Word Pro-gram Flowchart and Pseudo Code, for the flow-chart for using the Double Word Programcommand.

Clear Status Register Command

The Clear Status Register command can be usedto reset bits 1, 3, 4 and 5 in the Status Register to‘0’. One bus write cycle is required to issue theClear Status Register command.

The bits in the Status Register do not automatical-ly return to ‘0’ when a new Program or Erase com-mand is issued. The error bits in the StatusRegister should be cleared before attempting anew Program or Erase command.

Program/Erase Suspend Command

The Program/Erase Suspend command is used topause a Program or Erase operation. One buswrite cycle is required to issue the Program/Erasecommand and pause the Program/Erase control-ler.

During Program/Erase Suspend the Command In-terface will accept the Program/Erase Resume,Read Array, Read Status Register, Read Electron-ic Signature and Read CFI Query commands. Ad-ditionally, if the suspend operation was Erase thenthe Program, Block Lock, Block Lock-Down orProtection Program commands will also be ac-cepted. The block being erased may be protectedby issuing the Block Protect, Block Lock or Protec-tion Program commands. When the Program/Erase Resume command is issued the operationwill complete. Only the blocks not being erasedmay be read or programmed correctly.

During a Program/Erase Suspend, the device canbe placed in a pseudo-standby mode by takingChip Enable to VIH. Program/Erase is aborted ifReset turns to VIL.

See Appendix C, Figure 19, Program Suspend &Resume Flowchart and Pseudo Code, and Figure21, Erase Suspend & Resume Flowchart andPseudo Code for flowcharts for using the Program/Erase Suspend command.

Program/Erase Resume Command

The Program/Erase Resume command can beused to restart the Program/Erase Controller aftera Program/Erase Suspend operation has pausedit. One Bus Write cycle is required to issue thecommand. Once the command is issued subse-quent Bus Read operations read the Status Reg-ister.

See Appendix C, Figure 19, Program Suspend &Resume Flowchart and Pseudo Code, and Figure21, Erase Suspend & Resume Flowchart andPseudo Code for flowcharts for using the Program/Erase Resume command.

Protection Register Program Command

The Protection Register Program command isused to Program the 64 bit user One-Time-Pro-grammable (OTP) segment of the Protection Reg-ister. The segment is programmed 16 bits at atime. When shipped all bits in the segment are setto ‘1’. The user can only program the bits to ‘0’. Two write cycles are required to issue the Protec-tion Register Program command.

■The first bus cycle sets up the Protection Register Program command.

■The second latches the Address and the Data to be written to the Protection Register and starts the Program/Erase Controller.

Read operations output the Status Register con-tent after the programming has started.

The segment can be protected by programming bit1 of the Protection Lock Register. Bit 1 of the Pro-tection Lock Register protects bit 2 of the Protec-tion Lock Register. Programming bit 2 of theProtection Lock Register will result in a permanentprotection of the Security Block (see Figure 6, Se-curity Block and Protection Register MemoryMap). Attempting to program a previously protect-ed Protection Register will result in a Status Reg-ister error. The protection of the ProtectionRegister and/or the Security Block is not revers-ible.

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The Protection Register Program cannot be sus-pended. See Appendix C, Figure 23, ProtectionRegister Program Flowchart and Pseudo Code,for the flowchart for using the Protection RegisterProgram command.Block Lock Command

The Block Lock command is used to lock a blockand prevent Program or Erase operations fromchanging the data in it. All blocks are locked atpower-up or reset.

Two Bus Write cycles are required to issue theBlock Lock command.

■The first bus cycle sets up the Block Lock command.

■The second Bus Write cycle latches the block address.

The lock status can be monitored for each blockusing the Read Electronic Signature command.Table. 10 shows the protection status after issuinga Block Lock command.

The Block Lock bits are volatile, once set they re-main set until a hardware reset or power-down/power-up. They are cleared by a Blocks Unlockcommand. Refer to the section, Block Locking, fora detailed explanation.Block Unlock Command

The Blocks Unlock command is used to unlock ablock, allowing the block to be programmed orerased. Two Bus Write cycles are required to is-sue the Blocks Unlock command.

The first bus cycle sets up the Block Unlock command.

■The second Bus Write cycle latches the block address.

The lock status can be monitored for each blockusing the Read Electronic Signature command.Table. 10 shows the protection status after issuinga Block Unlock command. Refer to the section,Block Locking, for a detailed explanation.Block Lock-Down Command

A locked block cannot be Programmed or Erased,low, VILIH, the Lock-Downfunction is disabled and the locked blocks can beindividually unlocked by the Block Unlock com-mand.

Two Bus Write cycles are required to issue theBlock Lock-Down command.

■The first bus cycle sets up the Block Lock command.

■The second Bus Write cycle latches the block address.

The lock status can be monitored for each blockusing the Read Electronic Signature command.Locked-Down blocks revert to the locked (and notlocked-down) state when the device is reset onpower-down. Table. 10 shows the protection sta-tus after issuing a Block Lock-Down command.Refer to the section, Block Locking, for a detailedexplanation.

■

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Table 4. Commands

Bus Write Operations

Commands

No. of Cycles

1st CycleBus Op.WriteWriteWriteWriteWriteWriteWriteWriteWriteWriteWriteWriteWriteWrite

2nd Cycle

Bus Op.Read Read Read Read WriteWriteWrite

3nd Cycle

Data DataStatus Register

XXXXXXXXXXXXXX

FFh70h90h 98h 20h40h or 10h30h50hB0hD0h60h60h60hC0h

AddrRead AddrX

Bus Op.

AddrData

Read Memory ArrayRead Status RegisterRead Electronic SignatureRead CFI QueryEraseProgram

Double Word Program(3)Clear Status RegisterProgram/Erase SuspendProgram/Erase ResumeBlock LockBlock UnlockBlock Lock-DownProtection Register Program

1+1+1+1+2231112222

Signature

Signature

Addr (2)CFI AddrBlock AddrAddrAddr 1

QueryD0hData InputData Input

Write

Addr 2

Data Input

WriteWriteWriteWrite

Block AddressBlock AddressBlock AddressAddress

01hD0h2FhData Input

Note:1.X = Don't Care.

2.The signature addresses are listed in Tables 5, 6 and 7.

3.Addr 1 and Addr 2 must be consecutive Addresses differing only for A0.

Table 5. Read Electronic Signature

CodeManufacture. CodeDevice Code

Note:

IH.

DeviceEVIL

GVILVILVIL

WVIHVIHVIH

A0VILVIHVIH

A1VILVILVIL

A2-A7000

A8-A19Don't CareDon't CareDon't Care

DQ0-DQ720hCEhCFh

DQ8-DQ15

00h88h88h

M28W160CTM28W160CB

VILVIL

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Table 6. Read Block Lock Signature

Block StatusLocked BlockUnlocked BlockLocked-Down Block

VILVILVIL

VILVILVIL

VIHVIHVIH

A0VILVILVIL

A1VIHVIHVIH

A2-A7000

A8-A11

A12-A19

DQ010X (1)

DQ1001

DQ2-DQ15

00h00h00h

Don't CareBlock AddressDon't CareBlock AddressDon't CareBlock Address

Note:1.A Locked-Down Block can be locked "DQ0 = 1" or unlocked "DQ0 = 0"; see Block Locking section.

Table 7. Read Protection Register and Lock Register

WordLockUnique ID 0Unique ID 1Unique ID 2Unique ID 3OTP 0OTP 1OTP 2OTP 3

VILVILVILVILVILVILVILVILVIL

VILVILVILVILVILVILVILVILVIL

VIHVIHVIHVIHVIHVIHVIHVIHVIH

A0-A780h81h82h83h84h85h86h87h88h

A8-A19Don't CareDon't CareDon't CareDon't CareDon't CareDon't CareDon't CareDon't CareDon't Care

DQ00ID dataID dataID dataID dataOTP dataOTP dataOTP dataOTP data

DQ1OTP Prot. dataID dataID dataID dataID dataOTP dataOTP dataOTP dataOTP data

DQ2Security prot. dataID dataID dataID dataID dataOTP dataOTP dataOTP dataOTP data

DQ3-DQ7DQ8-DQ1500hID dataID dataID dataID dataOTP dataOTP dataOTP dataOTP data

00hID dataID dataID dataID dataOTP dataOTP dataOTP dataOTP data

Table 8. Program, Erase Times and Program/Erase Endurance Cycles

Parameter

Word ProgramDouble Word ProgramMain Block Program

Test ConditionsVPP = VDDVPP = 12V ±5%VPP = 12V ±5%VPP = VDDVPP = 12V ±5%VPP = VDDVPP = 12V ±5%VPP = VDDVPP = 12V ±5%VPP = VDD

100,00020

M28W160C

Min

10100.160.320.020.04110.80.8

200200554410101010

Unitµsµssssssssscyclesyears

Parameter Block Program

Main Block Erase

Parameter Block Erase

Program/Erase Cycles (per Block)Data Retention

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BLOCK LOCKING

The M28W160C features an instant, individualblock locking scheme that allows any block to belocked or unlocked with no latency. This lockingscheme has three levels of protection.

■Lock/Unlock - this first level allows software-only control of block locking.

■

Lock-Down - this second level requires hardware interaction before locking can be changed.

VPP ≤ VPPLK - the third level offers a complete hardware protection against program and erase on all blocks.

■

The lock status of each block can be set toLocked, Unlocked, and Lock-Down. Table 10, de-DQ1, DQ0), and Appendix C, Figure 22, shows aflowchart for the locking operations.Reading a Block’s Lock Status

The lock status of every block can be read in theRead Electronic Signature mode of the device. Toenter this mode write 90h to the device. Subse-quent reads at the address specified in Table 6,will output the lock status of that block. The lockstatus is represented by DQ0 and DQ1. DQ0 indi-cates the Block Lock/Unlock status and is set bythe Lock command and cleared by the Unlockcommand. It is also automatically set when enter-ing Lock-Down. DQ1 indicates the Lock-Down sta-tus and is set by the Lock-Down command. Itcannot be cleared by software, only by a hardwarereset or power-down.

The following sections explain the operation of thelocking system.Locked State

The default status of all blocks on power-up or af-ter a hardware reset is Locked (states (0,0,1) or(1,0,1)). Locked blocks are fully protected fromany program or erase. Any program or erase oper-ations attempted on a locked block will return anerror in the Status Register. The Status of aLocked block can be changed to Unlocked orLock-Down using the appropriate software com-mands. An Unlocked block can be Locked by issu-ing the Lock command.Unlocked State

Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)),can be programmed or erased. All unlockedblocks return to the Locked state after a hardwarereset or when the device is powered-down. Thestatus of an unlocked block can be changed toLocked or Locked-Down using the appropriate

software commands. A locked block can be un-locked by issuing the Unlock command.Lock-Down State

Blocks that are Locked-Down (state (0,1,x))areprotected from program and erase operations (asfor Locked blocks) but their lock status cannot bechanged using software commands alone. ALocked or Unlocked block can be Locked-Down byissuing the Lock-Down command. Locked-Downblocks revert to the Locked state when the deviceis reset or powered-down.

IL), the blocks in theLock-Down state (0,1,x) are protected from pro-gram, erase and protection status changes. WhenIH) the Lock-Down function is disabled(1,1,1) and Locked-Down blocks can be individu-ally unlocked to the (1,1,0) state by issuing thesoftware command, where they can be erased andprogrammed. These blocks can then be relockedpreviously Locked-Down return to the Lock-Downstate (0,1,x) regardless of any changes maderesets all blocks , including those in Lock-Down, tothe Locked state.

Locking Operations During Erase SuspendChanges to block lock status can be performedduring an erase suspend by using the standardlocking command sequences to unlock, lock orlock-down a block. This is useful in the case whenanother block needs to be updated while an eraseoperation is in progress.

To change block locking during an erase opera-tion, first write the Erase Suspend command, thencheck the status register until it indicates that theerase operation has been suspended. Next writethe desired Lock command sequence to a blockand the protection status will be changed. Aftercompleting any desired lock, read, or program op-erations, resume the erase operation with theErase Resume command.

If a block is locked or locked-down during an erasesuspend of the same block, the locking status bitswill be changed immediately, but when the eraseis resumed, the erase operation will complete.Locking operations cannot be performed during aprogram suspend. Refer to Appendix D, Com-mand Interface and Program/Erase ControllerState, for detailed information on which com-mands are valid during erase suspend.

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