Abstract — Reliability of systems used in space, avionic and biomedical applications is highly critical. Such systems consist of an analog front-end to collect data, an Analog-to-Digital Converter (ADC) to convert the collected data to digital form and a

Fig.3.SuccessiveApproximationarchitecture

Fig.1.A ash

ADC

ENC EncoderCLK Clock

INT Interpolator

SHA Sample & Hold AmpliflierREF Reference Voltage Generator

FA* Folding AmpliflierC* ComparatorL* Latch

Fig.4.SuccessiveApproximationADC

Fig.2.A4-bitFoldingandInterpolatingADC

II.ANALOG-TO-DIGITALCONVERTERS

AnalogtoDigitalConvertersareintegralpartsofdataacqui-sitionsystemsandactasaninterfacebetweenanalogblocksthatacquirethedataanddigitalblocksthatprocessthedata.ADCscanbebroadlyclassi edintohigh-speedandhigh-accuracyarchitectures.High-speedarchitecturesinclude ash,foldingandinterpolating,pipelined,multi-stepandinterleavedADCs[8].High-accuracyarchitecturesincludesuccessiveap-proximation,delta-sigmaandintegratingADCs[8].Thesetwocategoriestradeoffspeedvsaccuracy.Basedonthedemandsoftheapplication,oneoftheseADCscanbechosenaftercarefullyweighingthetradeoffs.Thefollowingsectionsbrie ydescribetheworkingoftheADCswhichhavebeenaddressedinthiswork.

A.FlashADC

Thisarchitectureisconceptuallythesimplestandpotentiallythefastest.Itemploys“parallelism”and“distributed”samplingtoachievehighconversionspeeds.Figure1showsablockdi-agramofanm-bit ashADC.Thecircuitconsistsof2mcom-parators,aresistorladdercomprising2mequalsegmentsandadecoder.Theladdersubdividesthemainreferenceinto2mequallyspacedvoltages,andthecomparatorscomparethein-putsignalwiththesevoltages.Forexample,iftheanaloginputisbetweenVjandVj+1,comparatorsA1throughAjproduce1sattheir

outputswhiletherestgenerate0s.Consequently,thecomparatoroutputsconstituteathermometercodewhichisconvertedtobinarybythedecoder.

B.FoldingandInterpolatingADC

Thelargeinputcapacitanceposedbythecomparatorsattheinputof ashADCsledtotheadventoffoldingandinterpolat-ing(FI)ADCs[9].FIADCsfoldtheinformationrepresentedbythereferencevoltageswhichcharacterizethequantizationlevels.Figure2showstheblockdiagramofa4-bitfoldingandinterpolatingADC.TheFAblocksinFigure2arefoldingam-pli ers,eachoneofwhichisaseriesofcross-coupleddifferen-tialstages[9].Thesampleandholdampli er(SHA)samplestheinputandfeedsittotwofoldingampli ers(FA1andFA2)andacomparator(CM)whichgeneratesthemostsigni cantbit.TheINTblockinterpolatesbetweenthefoldingampli eroutputs.TheINTblockoutputisfedtotheencoder(ENC)whichgeneratesthethreeleastsigni cantbitsofthe naldigi-taloutput.

C.SuccessiveApproximationADC

TheSuccessiveApproximation(SA)ADCsprogresslikeabinarysearchalgorithmtoarriveatthe naldigitaloutputwithanerrorofnomorethanhalftheleastsigni cantbit.Figure3illustratesthesuccessiveapproximationarchitecture,whichconsistsofafront-endSHA,acomparator,aregister(shift)andaDigital-to-AnalogConverter(DAC).The(shift)registerholdsthebitsthathavebeenconvertedstartingfromthemostsigni cantbit(MSB).ThisdigitalpatternisthenconvertedbytheDACtoanalogandthisvalueiscomparedagainsttheheldinput.Theoutputofthecomparatordecidesthevalueofthenextbit.Thus,the nalm-bitdigitalpatternisgeneratedinsuchamannerstartingfromtheMSBtotheleastsigni cantbittakingmcyclestogenerateanm-bitoutput.SuccessiveapproximationconvertersthatincorporatecapacitorDACsareusuallybasedonthechargeredistributionprinciple.Figure4showstheblockdiagramofachargeredistributionimplemen-tationofthesuccessiveapproximation(SA)[10]ADC.Forthiswork,anSAADCbasedonchargeredistributionwasimple-mented.TheprinciplecanbeillustratedusingFigure4,wheretheDACconsistsofbinary-weightedcapacitorsC1···Cn 1