Verilog HDL 课程设计报告 四人抢答器电路设计 河海大学

河海大学计算机与信息学院（常州）

课程设计报告

题 目 学 号 授课班号学生姓名同组成员 指导教师

完成时间

四人抢答器电路设计

摘要

Verilog HDL课程设计的主要动机是1.培养综合运用知识和独立开展实践创新的能力；2.通过完成四人抢答器电路设计，使学生不但能够将课堂上学到的理论知识与实际应用结合起来，而且能够对分析、解决实际的数字电路问题进一步加深认识，为今后能够独立进行某些数字应用系统的开发设计工作打下一定的基础；3.通过搭建调试电路，进一步熟悉相关仪器设备的使用；4.通过Verilog程序的编写，进一步熟悉Verilog HDL的语法知识；5.规范化训练学生撰写技术研究报告，提高书面表达能力。

四人抢答器电路设计的主要问题在于各个模块的正确分配，从而使设计出的电路更加符合要求。为了使各个模块能够正确分配，在程序开始设计之前，必须反复推敲本组的设计方案并设计好各个模块的方框图。如果一切都设计好之后，那么最后的电路会具有抢答第一信号鉴别和锁存功能、主持人清屏功能、30秒倒计时功能、蜂鸣器报警功能。

实现四人抢答器的预期功能需要：1.将任务分成若干模块，查阅相关论文资料，分模块调试和完成任务；2.遇到本组内解决不了的问题，及时和其他小组交流或询问老师；3.进行模块调试时，根据试验箱上现象的不同及时调整相关程序的内容。

本次课程设计的实现的重要结果1.完成了实验环境搭建；2.实现了一四人抢答器，有人抢答成功后，其他人再抢答无效；3.通过蜂鸣器响1秒来提示抢答成功，并在数码管上显示抢答者的序号；4.主持人通过按键清除抢答信息，并开始30秒的答题倒计时，当倒计时结束时，通过蜂鸣器响1秒来提示回答问题时间到，此时可以开始新一轮的抢答。

当然，本次课程设计还有诸多不足之处，我们已经力求改进以求设计的实用性及完美性。

关键字：Verilog HDL 方框图 QuartusII 抢答器

Abstract

The main motivations of the Verilog HDL curriculum design including five aspects. The first of them is cultivating the capabilities of integrated use of knowledge and carrying out practical innovation independently. Secondly, by completing four people Responder circuit design, students can not only apply the theories what they have learned in classes to the practical application, but also deepen the understanding of analyzing and solving the question about practical digital circuit, which can form the foundation for carrying out the development and design work of some digital applications systems in the future. Thirdly, we become more familiar with the use of the equipment by building debug circuitry. Fourthly, by writing Verilog program, we will be more skilled in Verilog HDL syntax knowledge. The last one of them is training students to write a technical report standardized to improve writing skills.

The main problem of it is that the correct allocation of the various modules, so that the circuit is more in line with the requirements. In order to assign each module correctly, we must scrutiny the design repeatedly and finish the block diagram of each module before we began the program. If all designed are ok, the final circuit will have the abilities in identifying and latching the first signal, clearing screen with the host, 30-second countdown function, buzzer alarm function.

Achieving the intended function of the four-person Responder need: 1. Task is divided into a number of modules and having access to relevant information papers, sub-module debugging and completing the task; 2. Solving the problem in a timely manner and communicating with other groups or asking a teacher; 3. When debugging module, we should adjust of the contents of the relevant procedures on the time depending on the different phenomenon.

The curriculum design achieved important results including: http://pleting structures of experimental environment; 2. Achieving a four people Responder and others cannot answer in invalid after someone answered in success; 3. With buzzer seconds to prompt answer in success, and display the answer in the serial number on the digital; 4. The host clears the information, and begin to answer 30 seconds countdown time prompted to answer questions by one second buzzer, when the countdown is end, a new round will start.

Of course, during the curriculum design, there are still many inadequacies, we have sought to improve the practicality and perfection.

Key word: Verilog HDL Block diagram QuartusII Responder

1 系统设计

1.1 要求的设计目标

（1）实现一四人抢答器，有人抢答成功后，其他人再抢答无效； （2） 通过蜂鸣器响1秒来提示抢答成功，并在数码管上显示抢答者的序号； （3）主持人通过按键清除抢答信息，并开始30秒的答题倒计时，当倒计时结束时，通过蜂鸣器响1秒来提示回答问题时间到，此时可以开始新一轮的抢答。 1.2 方案的对比分析与确定

我们通过搜索资料，并且依据所学知识，为清晰明了简便的设计出想达到的目标，最终我们采用设计的总体方案是将整个任务分成3个模块即分频模块、抢答及报警模块、倒计时并报警模块。 1.3 电路方框图及说明

图1电路方框图及说明

1.4 电路设计及说明 1.4.1 分频模块

因为试验箱上的时钟是50M的，而倒计时模块中要用到1hz和1khz的时钟，所以要对50M时钟进行分频产生1hz和1khz的时钟，分频模块程序如下： modu …… 此处隐藏：6737字，全部文档内容请下载后查看。喜欢就下载吧 ……