数字集成电路第十章
时间：2025-01-11
西安邮电学院数字计程电路PPT课件
Digital Integrated CircuitsA Design PerspectiveJan M. Rabaey Anantha Chandrakasan Borivoje Nikoli
Timing IssuesJanuary 2003EE141 © Digital Integrated
Circuits2nd
Timing Issues
西安邮电学院数字计程电路PPT课件
Synchronous Timing
CLK In R1 Cin Combinational Logic Cout R2
Out
EE141 © Digital Integrated
Circuits2nd
Timing Issues
西安邮电学院数字计程电路PPT课件
Timing Definitions
EE141 © Digital Integrated
Circuits2nd
Timing Issues
西安邮电学院数字计程电路PPT课件
Latch ParametersD Q Clk T Clk D tc-q PWm tsu
tholdtd-q
Q
Delays can be different for rising and falling data transitionsEE141 © Digital Integrated
Circuits2nd
Timing Issues
西安邮电学院数字计程电路PPT课件
Register ParametersD Q Clk T Clk D tsu Q tc-q thold
Delays can be different for rising and falling data transitionsEE141 © Digital Integrated
Circuits2nd
Timing Issues
西安邮电学院数字计程电路PPT课件
Clock Uncertainties4 Power Supply 3 Interconnect Devices 6 Capacitive Load 7 Coupling to Adjacent Lines
2
5 Temperature 1 Clock Generation
Sources of clock uncertaintyEE141 © Digital Integrated
Circuits2nd
Timing Issues
西安邮电学院数字计程电路PPT课件
Clock Nonidealities
Clock skew Spatial variation in temporally equivalent clock edges; deterministic + random, tSK
Clock jitter Temporal variations in consecutive edges of the clock signal; modulation + random noise Cycle-to-cycle (short-term) tJS Long term tJL
Variation of the pulse width Important for level sensitive clocking
EE141 © Digital Integrated
Circuits2nd
Timing Issues
西安邮电学院数字计程电路PPT课件
Clock Skew and JitterClktSK
Clk
tJS
Both skew and jitter affect the effective cycle time Only skew affects the race margin
EE141 © Digital Integrated
Circuits2nd
Timing Issues
西安邮电学院数字计程电路PPT课件
Clock Skew# of registers Earliest occurrence of Clk edge Nominal – /2 Latest occurrence of Clk edge Nominal + /2
Insertion delay Max Clk skew
Clk delay
9
EE141 © Digital Integrated
Circuits2nd
Timing Issues
西安邮电学院数字计程电路PPT课件
Positive and Negative SkewIn CLK R1 D Q tCLK1 delay (a) Positive skew R1 D Q tCLK1 delay(b) Negative skew10
Combinational Logic
R2 D Q tCLK2delay Combinational Logic
R3D Q
tCLK3
In
Combinational Logic
R2 D Q tCLK2 delay Combinational Logic
R3 D Q tCLK3 CLK
EE141 © Digital Integrated
Circuits2nd
Timing Issues
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Positive SkewTCLK + d CLK1 1d
TCLK
3
CLK2
2d + th
4
Launching edge arrives before the receiving edge11
EE141 © Digital Integrated
Circuits2nd
Timing Issues
西安邮电学院数字计程电路PPT课件
Negative SkewTCLK + d
CLK1
1
TCLK
3
CLK2
2
d
4
Receiving edge arrives before the launching edge12
EE141 © Digital Integrated
Circuits2nd
Timing Issues
西安邮电学院数字计程电路PPT课件
Timing ConstraintsIn R1D Q
R2 Combinational LogicD Q
CLK tc - q
tCLK1 tlogictlogic, cd tc - q, cd tsu, thold
tCLK2
Minimum cycle time: T - = tc-q + tsu + tlogicWorst case is when receiving edge arrives early (positive )EE141 © Digital Integrated
Circuits2nd
Timing Issues
西安邮电学院数字计程电路PPT课件
Timing ConstraintsIn R1D Q
R2 Combinational LogicD Q
CLK tc - q
tCLK1 tlogictlogic, cd tc - q, cd tsu, thold
tCLK2
Hold time constraint: t(c-q, cd
) + t(logic, cd) > thold + Worst case is when receiving edge arrives late Race between data and clockEE141 © Digital Integrated
Circuits2nd
Timing Issues
西安邮电学院数字计程电路PPT课件
Impact of Jitter CLK
TC LK
t j it t er -tji t te r
In
R EGS
Com binat ional Logi c
C LK tc -q , tc -q, ts u, thol d tji t t e r
cd
t l og ic t l og ic , c d
EE141 © Digital Integrated
Circuits2nd
Timing Issues
西安邮电学院数字计程电路PPT课件
Longest Logic Path in Edge-Triggered SystemsTSU Clk TClk-Q TJI +
TLM T
Latest point of launching
Earliest arrival of next cycle
EE141 © Digital Integrated
Circuits2nd
Timing Issues
