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OTM8009A

CPT NW Panel Application note

1440x800 System-on-chip Driver for 480xRGBx800 Stripe TFT LCD

Dec. 13, 2011 Version 0.1

Table of Contents

1. CPT 3.97〞APPLICATION NOTE FOR NORMALLY WHITE CELL...................................................................................3

1.1. APPLICATION CIRCUIT........................................................................................................................................................................4 1.2. INITIAL CODE.....................................................................................................................................................................................6

2. DISCLAIMER...................................................................................................................................................................13 3. REVISION HISTORY........................................................................................................................................................14

1. CPT 3.97〞APPLICATION NOTE FOR NORMALLY WHITE CELL

CPT Cell Model Name : CLAF040LE21

Product Description :3.97 inch 480xRGBx800 Stripe TFT-LCD

1.1. Application Circuit

VDDIO

1.0uF/4V

C1

VDD

2.2uF/6.3VC11N

2.2uF/6.3VC12N

2.2uF/6.3VC13N

2.2uF/6.3VC14N

2.2uF/6.3V

C2

C11P

C3

C12P

C4

C13P

C5

C14P

C6

VDDA

V2.2uF/10VC21N

2.2uF/6.3VC22N

2.2uF/6.3VC23N

2.2uF/6.3VC24N

2.2uF/6.3V

C7

C21P

C8

C22P

C9

C23P

C10

C24P

C11

NVDDA

2.2uF/10VC31N

2.2uF/6.3VC32N

2.2uF/6.3V

C12

C31P

C13

C32P

C14

VCL

2.2uF/6.3VC41N

1.0uF/16V

C15

C41P

C16

VGH

1.0uF/25VC51N

1.0uF/16V

C17

C51P

C18

VREF

1.0uF/4V

C20

VCOM

2.2uF/4V

C21

VDD_18V

2.2uF/4V

C22

DIOPWR

1.0uF/4V

C23

LVDSVDD

1.0uF/4V

C24

VDDP

1.0uF/4V

C25

VGL_REGC26(OPTIONAL)

1.0uF/20V

Interface application note:

External Pad Set

IM2 0 0 0 0 1 1 1 1

IM1 0 0 1 1 0 0 1 1

IM0 0 1 0 1 0 1 0 1

Interface format 80-series 8-bit MPU interface 80-series 16-bit MPU interface 80-series 24-bit MPU interface

RGB[8:8:8] + SPI RGB[8:8:8] + I2C

MIPI-DSI MDDI + SPI MDDI + I2C

Hardware control pin note:

SYMBOL LANSEL NBWSEL

VSEL

(DIOPWR voltage select) PSWAP

(Lanes Polarity swapping)

Pull Low"0" 1 Lane NW 1.2V Positive->Positive

CH0->D0 CH1->D1 CH0->D0 CH1-> X

Pull High"1" 2 Lane NB 1.8V

Positive->Negative

CH0->D1 CH1->D0 CH0-> X CH1->D0

Note

SW priority first.

For 2 Lanes use For 1 Lanes use

DSWAP

(Data Lanes swapping)

Note:

The cell mode(CLAF040LE21) connect NBWSEL pin to “1”(NB),now. It must be write command 21H to change Display inversion for NW.

VDD = 2.8V ; VDDIO = 1.8V

(VDD and VDDIO supply at the same time will be better)

for MIPI

for RGB

ADDRESS PARAMETER

FF00h FF01h FF02h FF80h FF81h FF03h 2100h B3A1h

B3A6h B3A7h

CE80h CE81h CE82h CE83h CE84h CE85h

CEA0h

1.2. Initial Code

ITEM

Command 2 Enable

Address Shift

ORISE

Command Enable

Address Shift

Address Shift

Address Shift

Address Shift CE8x

Address Shift CEAx

ADDRESS PARAMETER

FFh 80h 09h 01h 00h 80h FFh 80h 09h 00h 03h FFh 01h 21h 00h A1h B3h 10h 00h A6h B3h 2Bh 11h 00h 80h CEh 82h 01h 00h 81h 01h 00h 00h A0h CEh 18h

Note

For normally white

Panel timing setting start

80h 09h 01h 80h 09h 01h 10h 2Bh 11h 82h 01h 00h 81h 01h 00h 18h

OTM8009A

00h 03h 23h 00h 00h 00h 10h 00h 03h 24h 00h 00h 00h 00h B0h CEh 10h 01h 03h 23h 00h 00h 00h 10h 02h 03h 24h 00h 00h 00h 00h C7h CFh 00h 00h C6h CBh 04h 04h 00h C9h CBh 04h 00h

CEA1h CEA2h CEA3h CEA4h CEA5h CEA6h CEA7h CEA8h CEA9h CEA0Ah CEA0Bh CEA0Ch CEA0Dh

CEB0h CEB1h CEB2h CEB3h CEB4h CEB5h CEB6h CEB7h CEB8h CEB9h CEBAh CEBBh CEBCh CEBDh

CFC7h

CBC6h CBC7h

CBC9h

Address Shift CEBx

Address Shift CFCx

Address Shift CBCx

Address Shift CBCx

Address Shift

00h 03h 23h 00h 00h 00h 10h 00h 03h 24h 00h 00h 00h 10h 01h 03h 23h 00h 00h 00h 10h 02h 03h 24h 00h 00h 00h 00h 04h 04h 04h

OTM8009A

DBh CBh 04h 04h 00h DEh CBh 04h 00h 86h CCh 0Ch 0Ah 00h 89h CCh 02h 00h A1h CCh 0Bh 09h 00h A4h CCh 01h 00h B6h CCh 09h 0Bh 00h B9h CCh 01h 00h D1h CCh 0Ah 0Ch 00h D4h CCh 02h

CBDBh CBDCh

CBDEh

CC86h CC87h

CC89h

CCA1h CCA2h

CCA4h

CCB6h CCB7h

CCB9h

CCD1h CCD2h

CCD4h

CBDx

Address Shift CBDx

Address Shift CC8x

Address Shift CC8x

Address Shift CCAx

Address Shift CCAx

Address Shift CCBx

Address Shift CCBx

Address Shift CCDx

Address Shift CCDx

04h 04h 04h 0Ch 0Ah 02h 0Bh 09h 01h 09h 0Bh 01h 0Ah 0Ch 02h

Panel timing setting end

OTM8009A

00h 00h D8h 9Fh 9Fh 00h 82h C5h A3h 00h 90h C5h D6h EAh 01h 00h 00h 00h 00h 00h E1h 20h 21h 22h 0Bh 04h 17h 0Ch 0Dh 00h 04h 03h 06h 0Dh 24h 21h 1Ah 00h 00h E2h 20h 21h

D800h D801h C582h C590h C591h C592h 0000h E100h E101h E102h E103h E104h E105h E106h E107h E108h E109h E10Ah E10Bh E10Ch E10Dh E10Eh E10Fh E200h E201h

Address Shift

Address Shift

Address Shift

Address Shift

Address Shift

Gamma(2.2+) setting

Address Shift

Gamma(2.2+) setting

9Fh 9Fh A3h D6h EAh 01h 00h 20h 21h 22h 0Bh 04h 17h 0Ch 0Dh 00h 04h 03h 06h 0Dh 24h 21h 1Ah 20h 21h

GVDD setup NGVDD setup

REG-pump23

Pump setting

Pump setting(VGH/VGL) Pump45

Gamma setting start.

OTM8009A

22h 0Bh 04h 17h 0Ch 0Dh 00h 04h 03h 06h 0Dh 24h 21h 1Ah 00h 00h 00h 00h B1h C5h A9h 00h 00h 00h 11h 29h

E202h E203h E204h E205h E206h E207h E208h E209h E20Ah E20Bh E20Ch E20Dh E20Eh E20Fh 0000h C5B1h

0000h 1100h 2900h

22h 0Bh 04h 17h 0Ch 0Dh 00h 04h 03h 06h 0Dh 24h 21h 1Ah 00h A9h 00h

Gamma setting end

DC voltage setting

Initial code end

Address Shift

Address Shift

GVDD output

Address Shift

WAIT 50ms SLEEP OUT WAIT 150ms Display On

*Note:

SPI Write mode:

The write mode of the interface means the micro controller writes commands and data to the OTM8009A. The serial interface is initialized when CSX is high. In this state, SCL clock pulse or SDI data have no effect. A falling edge on CSX enables the serial interface and indicates the start of data transmission.

When CSX is high, SCL clock is ignored. During the high time of CSX the serial interface is initialized. At the falling CSX edge, SCL can be high or low (See Figure 6.6.1.1). SDI / SDO is sampled at the rising edge of SCL. R/W indicates, whether the byte is read command (R/W = '1') or write command (R/W = '0'). It is sampled when first rising SCL edge. If CSX stays low after the last bit of command/data byte, the serial interface expects the R/W bit of the next byte at the next rising edge of SCL

1.2.2 Power on follow chart

Note 1:

Write Register 0xFF02h with parameter 0x0001h

2. DISCLAIMER

The information appearing in this publication is believed to be accurate.

Integrated circuits sold by ORISE Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. ORISE Technology makes no warranty, express, statutory imlied or by description regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. URTHERMORE, ORISE Technology MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. ORISE Technology reserves the right to halt production or alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by ORISE Technology for such applications. Please note that application circuits illustrated in this document are for reference purposes only.

3. REVISION HISTORY

Date Dec. 13, 2011

Revision #

0.1

Original

Description Page -