8421码转余3码 quartus II (FPGA) 数字电路课程设计
发布时间：2024-11-21
8421码转余3码 quartus II (FPGA)
FPGA 8421码转余三码
8421码转余3码 quartus II (FPGA)
quartusII代码
library ieee;
use ieee.std_logic_1164.all;
8421码转余3码 quartus II (FPGA)
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity key_led is
port (
key_in : in std_logic_vector (3 downto 0);
led_out : out std_logic_vector (7 downto 0)
);
end entity;
architecture key_led_arch of key_led is
begin
process(key_in)
begin
case key_in is
when "0000" => led_out <= "11110010"; ————3
when "0001" => led_out <= "01100110"; ————4
when "0010" => led_out <= "10110110"; ————5
when "0011" => led_out <= "10111110"; ————6
when "0100" => led_out <= "11100000"; ————7
when "0101" => led_out <= "11111110"; ————8
when "0110" => led_out <= "11110110"; ————9
8421码转余3码 quartus II (FPGA)
when "0111" => led_out <= "11101110"; ————A
when "1000" => led_out <= "00111110"; ————b
when "1001" => led_out <= "10011100"; ————C
when others => led_out <= "11111111";——————全亮（包括小数点）
end case;
end process;
end architecture;
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