CD74HC4052PWTG4中文资料(2)

元器件交易网’HC4051,’HCT4051,’HC4052, CD74HCT4052,’HC4053, CD74HCT4053 PinoutsCD54HC4051, CD54HCT4051 (CERDIP) CD74HC4051 (PDIP, SOIC, SOP, TSSOP) CD74HCT4051 (PDIP, SOIC) TOP VIEWCHANNEL IN/OUT COM OUT/IN CHANNEL IN/OUT A4 1 A6 2 A 3 A7 4 A5 5 E 6 VEE 7 GND 8 16 VCC 15 A2 14 A1 13 A0 12 A3 11 S0 10 S1 9 S2 ADDRESS SELECT CHANNEL IN/OUT CHANNEL IN/OUT

CD54HC4052 (CERDIP) CD74HC4052 (PDIP, SOIC, SOP, TSSOP) CD74HCT4052 (PDIP, SOIC) TOP VIEWB0 1 B2 2 16 VCC 15 A2 14 A1 13 AN 12 A0 11 A3 10 S0 9 S1 CHANNEL IN/OUT COM OUT/IN CHANNEL IN/OUT

COM OUT/IN BN 3 CHANNEL IN/OUT B3 4 B1 5 E 6 VEE 7 GND 8

CD54HC4053 (CERDIP) CD74HC4053 (PDIP, SOIC, SOP, TSSOP) CD74HCT4053 (PDIP, SOIC, TSSOP) TOP VIEWB1 1 CHANNEL IN/OUT B0 2 C1 3 COM OUT/IN CN 4 IN/OUT C0 5 E 6 VEE 7 GND 8 16 VCC 15 BN 14 AN 13 A1 12 A0 11 S0 10 S1 9 S2 COM OUT/IN COM OUT/IN CHANNEL IN/OUT

元器件交易网’HC4051,’HCT4051,’HC4052, CD74HCT4052,’HC4053, CD74HCT4053 Functional Diagram of HC/HCT4051CHANNEL IN/OUT VCC 16 A7 4 A6 2 A5 5 A4 1 A3 12 A2 15 A1 14 A0 13 TG

TG S0 11 TG

S1

10 LOGIC LEVEL CONVERSION BINARY TO 1 OF 8 DECODER WITH ENABLE

TG 3 TG A COMMON OUT/IN

S2

9

TG

TG E 6 TG

8 GND

7 VEE

TRUTH TABLE HC/HCT4051 INPUT STATES ENABLE L L L L L L L L H X= Don’t care S2 L L L L H H H H X S1 L L H H L L H H X S0 L H L H L H L H X“ON” CHANNELS A0 A1 A2 A3 A4 A5 A6 A7 None

元器件交易网’HC4051,’HCT4051,’HC4052, CD74HCT4052,’HC4053, CD74HCT4053 Functional Diagram of’HC4052, CD74HCT4052A CHANNELS IN/OUT A3 VCC 16 TG 11 A2 15 A1 14 A0 12

TG

TG

S1

9

LOGIC LEVEL CONVERSION

BINARY TO 1 OF 4 DECODER WITH ENABLE

TG

13

COMMON A OUT/IN COMMON B OUT/IN

TG

3

S0

10 TG

E

6 TG

TG 8 GND 7 VEE 1 B0 5 B1 2 B2 4 B3

B CHANNELS IN/OUT

TRUTH TABLE’HC4052, CD74HCT4052 INPUT STATES ENABLE L L L L H X= Don’t care S1 L L H H X S0 L H L H X“ON” CHANNELS A0, B0 A1, B1 A2. B2 A3, B3 None

元器件交易网’HC4051,’HCT4051,’HC4052, CD74HCT4052,’HC4053, CD74HCT4053 Functional Diagram of’HC4053, CD74HCT4053BINARY TO 1 OF 2 DECODERS WITH ENABLE IN/OUT C1 3 C0 5 B1 1 B0 2 A1 13 A0 12 TG 14

S0 11 TG A COMMON OUT/IN

VCC LOGIC LEVEL CONVERSION 16

TG S1 10 TG 15 B COMMON OUT/IN

S2

9

TG 4 TG C COMMON OUT/IN

E

6

8 GND

7 VEE

TRUTH TABLE’HC4053, CD74HCT4053 INPUT STATES ENABLE L L L L L L L L H X= Don’t care S0 L H L H L H L H X S1 L L H H L L H H X S2 L L L L H H H H X“ON” CHANNELS C0, B0, A0 C0, B0, A1 C0, B1, A0 C0, B1, A1 C1, B0, A0 C1, B0, A1 C1, B1, A0 C1, B1, A1 None

元器件交易网’HC4051,’HCT4051,’HC4052, CD74HCT4052,’HC4053, CD74HCT4053Absolute Maximum Ratings(Note 2)

Thermal InformationPackage Thermal Impedance,θJA (see Note 1): E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67oC/W M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73oC/W NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC

DC Supply Voltage, VCC - VEE . . . . . . . . . . . . . . . . . -0.5V to 10.5V DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to+7V DC Supply Voltage, VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . .+0.5V to -7V DC Input Diode Current, IIK For VI< -0.5V or VI> VCC+ 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Switch Diode Current, IOK For VI< VEE -0.5V or VI> VCC+ 0.5V . . . . . . . . . . . . . . . . .±20mA DC Switch Current, (Note 2) For VI> VEE -0.5V or VI< VCC+ 0.5V . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA DC VEE Current, IEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20mA NOTE:

1. The package thermal impedance is calculated in accordance with JESD 51-7.

Recommended Operating ConditionsPARAMETER

For maximum reliability, nominal operating conditions should be selected so that operation is always within the following ranges MIN MAX UNITS

Supply Voltage Range (For TA= Full Package Temperature Range), VCC (Note 2) CD54/74HC Types CD54/74HCT Types Supply Voltage Range (For TA= Full Package Temperature Range), VCC - VEE CD54/74HC Types, CD54/74HCT Types (See Figure 1) Supply Voltage Range (For TA= Full Package Temperature Range), VEE (Note 3) CD54/74HC Types, CD54/74HCT Types (See Figure 2) DC Input Control Voltage, VI Analog Switch I/O Voltage, VIS Operating Temperature, TA Input Rise and Fall Times, tr, tf 2V 4.5V 6V 0 0 0 1000 500 400 ns ns ns 0 GND VEE -55 -6 VCC VCC 125 V V VoC

2 4.5

6 5.5

V V

2

10

V

CAUTION: Stresses above those listed in“Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above

those indicated in the operational sections of this speci cation is not implied.

NOTES: 2. All voltages referenced to GND unless otherwise specified.. 3. In certain applications, the external load resistor current may include both VCC and signal line components. To avoid drawing VCC current when switch current flows into the transmission gate inputs, the voltage drop across the bidirectional switch must not exceed 0.6V (calculated from rON values shown in Electrical Specifications table). No VCC current will flow through RL if the switch current flows in …… 此处隐藏：15256字，全部文档内容请下载后查看。喜欢就下载吧 ……