GT2440开发板
时间：2025-03-11
嵌入式gt2440开发板介绍
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A
A
GT2440B CPU1 01-CPU1.Sch CPU2 02-CPU2.Sch CPU3 03-CPU3.Sch B
SDRAM 04-MEM.sch
CS8900 05-CS8900.sch
06-Audio.sch
Audio
07-UART_USB_ETC.sch
Interface 8-INTERFACE.sch
Power 9-POWER.sch
C
C
D
D
GT StudioPG CHECKED BY: ZH D APPROVED BY: YLCDRAWIN BY:
TITLE:DATE: DATE: DATE:
GT2440DWG NO.: SIZE: PCB NO.: REV:
BFILE: SHEET:
R 1OF
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嵌入式gt2440开发板介绍
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A R22P0R2202
A VDD33VP0R2201
BUS
BUS
4.7K J1OM0N0NLED01 nLED_1 N0NLED02 nLED_2 N0NGCS0 nGCS0 N0NGCS1 nGCS1 N0NGCS2 nGCS2 N0NLAN0CS nLAN_CS N0NGCS4 nGCS4 N0NGCS5 nGCS5 N0LNOE LnOE N0NWAIT nWAIT LnWE N0LNWE N0OM0
N0NXDACK0 nXDACK0 N0NLED03 nLED_3 N0NXDREQ0 nXDREQ0 N0NLED04 nLED_4
1 P0J1022 P0J1033P0J101
PCB PCBP0R3502
Nor Nand
CON3P0R3501
R35
4.7K U1A
nXDACK0/GPB9 P0U1A0K7 nXDACK1/GPB7 P0U1A0K6 nXDREQ0/GPB10 P0U1A0K5 nXDREQ1/GPB8
P0U1A0K2 K2 nXBACK/GPB5 P0U1A0L5 L5 nXBREQ/GPB6 P0U1A0F6 F6 nGCS0 P0U1A0B2 B2 nGCS1/GPA12 P0U1A0C3 C3 nGCS2/GPA13 P0U1A0C4 C4 nGCS3/GPA14 P0U1A0D3 D3 nGCS4/GPA15 P0U1A0C2 C2 nGCS5/GPA16 P0U1A0C5 C5 nOE P0U1A0E4 E4 nWAIT P0U1A0E6 E6 nWE P0U1A0T15 T15 OM0 P0U1A0R13 R13 OM1
P0U1A0L3
L3 K7 K6 K5
B
C1
1 P0X101 P0X102 2 1 2
N0LADDR0 LADDR0 N0LADDR1 LADDR1 N0LADDR2 LADDR2 N0LADDR3 LADDR3 N0LADDR4 LADDR4 N0LADDR5 LADDR5 N0LADDR6 LADDR6 N0LADDR7 LADDR7 N0LADDR8 LADDR8 N0LADDR9 LADDR9 N0LADDR10 LADDR10 N0LADDR11 LADDR11 N0LADDR12 LADDR12 N0LADDR13 LADDR13 N0LADDR14 LADDR14 N0LADDR15 LADDR15 N0LADDR16 LADDR16 N0LADDR17 LADDR17 N0LADDR18 LADDR18 N0LADDR19 LADDR19 N0LADDR20 LADDR20
TOUT0/GPB0 TOUT1/GPB1 P0U1A0J7 TOUT2/GPB2 P0U1A0K3 TOUT3/GPB3 P0U1A0K4 TCLK0/GPB4 P0U1A0U12 TCLK1/EINT19/GPG11
H12 P0U1A0H12 EXYCLK R9 P0U1A0R9 CLKOUT0/GPH9 P10 P0U1A0P10 CLKOUT1/GPH10 N14 P0U1A0N14 MPLLCAP P17 P0U1A0P17 UPLLCAP P13 P0U1A0P13 OM2 T13 P0U1A0T13 OM3 G14 P0U1A0G14 XTIpll G15P0U1A0G15 XTOpll M14 P0U1A0M14 XTIrtc L12P0U1A0L12 XTOrtc
C
N0LADDR24 LADDR24 N0LADDR25 LADDR25
R14 P0U1A0R14 AIN0 U17 P0U1A0U17 AIN1 R15 P0U1A0R15 AIN2 P15 P0U1A0P15 AIN3 T16 P0U1A0T16 AIN4/TSYM T17 P0U1A0T17 AIN5/TSYP R16 P0U1A0R16 AIN6/TSXM P16 P0U1A0P16 AIN7/TSXP U16 P0U1A0U16 Aref
F7 E7 B7 F8 C7 D8 E8 D7 G8 B8 A8 C8 B9 H8 E9 C9 D9 G9 F9 H9 D10 C10 H10 E10 C11 G10 D11
ADDR/GPA0 ADDR1 P0U1A0B7 ADDR2 P0U1A0F8 ADDR3 P0U1A0C7 ADDR4 P0U1A0D8 ADDR5 P0U1A0E8 ADDR6 P0U1A0D7 ADDR7 P0U1A0G8 ADDR8 P0U1A0B8 ADDR9 P0U1A0A8 ADDR10 P0U1A0C8 ADDR11 P0U1A0B9 ADDR12 Address P0U1A0H8 ADDR13 P0U1A0E9 ADDR14 P0U1A0C9 ADDR15 P0U1A0D9 ADDR16 P0U1A0G9 ADDR17 P0U1A0F9 ADDR18 P0U1A0H9 ADDR19 P0U1A0D10 ADDR20 P0U1A0C10 ADDR21 P0U1A0H10 ADDR22 P0U1A0E10 ADDR23 P0U1A0C11 ADDR24 P0U1A0G10 ADDR25 P0U1A0D11 ADDR26P0U1A0E7
P0U1A0F7
DMA
Chip Select
S3C2440 Data
ADC
Clock
Timer
P0U1A0D12 D12 DATA0 P0U1A0C12 C12 DATA1 P0U1A0E11 E11 DATA2 P0U1A0A13 A13 DATA3 P0U1A0F10 F10 DATA4 P0U1A0F11 F11 DATA5 P0U1A0C13 C13 DATA6 P0U1A0A14 A14 DATA7 P0U1A0D13 D13 DATA8 P0U1A0B15 B15 DATA9 P0U1A0A17 A17 DATA10 P0U1A0C14 C14 DATA11 P0U1A0D15 D15 DATA12 P0U1A0C15 C15
DATA13 P0U1A0D14 D14 DATA14 P0U1A0B17 B17 DATA15 P0U1A0C16 C16 DATA16 P0U1A0E15 E15 DATA17 P0U1A0E14 E14 DATA18 P0U1A0E13 E13 DATA19 P0U1A0E12 E12 DATA20 P0U1A0E16 E16 DATA21 P0U1A0F15 F15 DATA22 P0U1A0G13 G13 DATA23 P0U1A0E17 E17 DATA24 P0U1A0G12 G12 DATA25 P0U1A0F14 F14 DATA26 P0U1A0F12 F12 DATA27 P0U1A0G11 G11 DATA28 P0U1A0G16 G16 DATA29 P0U1A0H13 H13 DATA30 P0U1A0F13 F13 DATA31
N0LDATA0 LDATA0 N0LDATA1 LDATA1 N0LDATA2 LDATA2 N0LDATA3 LDATA3 N0LDATA4 LDATA4 N0LDATA5 LDATA5 N0LDATA6 LDATA6 N0LDATA7 LDATA7 N0LDATA8 LDATA8 N0LDATA9 LDATA9 N0LDATA10 LDATA10 N0LDATA11 LDATA11 N0LDATA12 LDATA12 N0LDATA13 LDATA13 N0LDATA14 LDATA14 N0LDATA15 LDATA15 N0LDATA16 LDATA16 N0LDATA17 LDATA17 N0LDATA18 LDATA18 N0LDATA19 LDATA19 N0LDATA20 LDATA20 N0LDATA21 LDATA21 N0LDATA22 LDATA22 N0LDATA23 LDATA23 N0LDATA24 LDATA24 N0LDATA25 LDATA25 N0LDATA26 LDATA26 N0LDATA27 LDATA27 N0LDATA28 LDATA28 N0LDATA29 LDATA29 N0LDATA30 LDATA30 N0LDATA31 LDATA31
B
P0C502 P0C501
P0X202
C5 15p
N0XTIPLL XTIpll
P0C602 P0C601
C6 15p
P0X201
X2 12MN0XTOPLL XTOpll
22pP0C102 P0C101 N0XTIRTC XTIrtc
X1 32.768kHzN0XTORTC XTOrtc
P0C202 P0C201
C2 22p
C
P0U1A0J6
P0U1A0J5
N0CLKOUT0 CLKOUT0 N0CLKOUT1 CLKOUT1 N0MPLLCAP MPLLCAP N0UPLLCAP UPLLCAP
VDD33V VDD33V R68P0R6802 P0C4002 P0C4001 P0C4102 P0C4101 N0MPLLCAP MPLLCAP N0UPLLCAP UPLLCAP
P0R6801
4.7K
N0GPB0 GPB0 GPB1 N0GPB1 L3MODE N0L3MODE N0L3DATA L3DATA N0L3CLOCK L3CLOCK N0EINT19 EINT19
N0AIN0 AIN0 N0AIN1 AIN1 N0AIN2 AIN2 N0AIN3 AIN3 N0TSYM TSYM N0TSYP TSYP N0TSXM TSXM N0TSXP TSXP
N0XTIPLL XTIpll N0XTOPLL XTOpll N0XTIRTC XTIrtc N0XTORTC XTOrtc
J6 J5 J7 K3 K4 U12
S3C2440X
C40 2n7
C41 680p
D
D
GT StudioDRAWIN BY:
TITLE:DATE: DATE: DATE: FILE: DWG NO.: SIZE: PCB NO.: REV:
PG CHECKED BY: ZH D APPROVED BY: YLC1 2 3 4 5
BSHEET:
R 1OF
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嵌入式gt2440开发板介绍
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VDD33VP0NR101 P0NR201 P0NR301 P0NR401 P0NR402
NR1
NR2
NR3
NR4
P0NR102
P0NR202
P0NR302
10K
10K
10K
10K
N0NCON NCON N0GPG13 GPG13
AGPIO_IO GPIO_IO GPIO_IO GPIO_IO GPIO_IO GPIO_IO GPIO_IO GPIO_IO GPIO_IO GPIO_IO
N0GPG14 GPG14 N0GPG15 GPG15 P0NR501 P0NR801
A
1K
1K
P0NR502
N0I2SLRCK I2SLRCK N0I2SSCLK I2SSCLK N0CDCLK CDCLK N0I2SSDI I2SSDI N0I2SSDO I2SSDO
GT2440开发板.doc
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