P4C198/198L, P4C198A/198AL

TRUTH TABLES

P4C198/LCEWEOEModeOutputHXXStandbyHigh ZLHHOutput InhibitHigh ZLHLREADDOUTL

L

X

WRITE

DIN

AC TEST CONDITIONS

Input Pulse LevelsGND to 3.0V

Input Rise and Fall Times3nsInput Timing Reference Level1.5VOutput Timing Reference Level1.5V

Output Load

See Figures 1 and 2

Figure 1. Output Load

* including scope and test fixture.

Note:

Because of the ultra-high speed of the P4C198/L and P4C198A/L, caremust be taken when testing this device; an inadequate setup can causea normal functioning part to be rejected as faulty. Long high-inductanceleads that cause supply bounce must be avoided by bringing the Vground planes directly up to the contactor fingers. A 0.01 µF high

CC andDocument # SRAM113 REV AP4C198A/LCE1CE2WEOEModeOutputHXXXStandbyHigh ZXHXXStandbyHigh ZLLHHOutput InhibitHigh ZLLHLREADDOUTL

L

L

X

WRITE

DIN

Figure 2. Thevenin Equivalent

frequency capacitor is also required between VCC and ground. To avoidsignal reflections, proper termination must be used; for example, a 50 test environment should be terminated into a 50 load with 1.73V(Thevenin Voltage) at the comparator input, and a 116 resistor mustbe used in series with DOUT to match 166 (Thevenin Resistance).

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