C Based System Level Design

Thomas Komarek

Agenda&System

level design challenges&SystemC - A modeling environment for hardware and software&CoCentricTM System Studio&Conclusions

System Level Design Challenges

System Level Design in the System-on-a-Chip World< 0.25µ Geometries

Manage the DetailsSystem on a Chip

Manage the ComplexityHigher Levels of Abstraction Design Reuse

SLD

Millions of Gates

Higher Design Complexity Requirements&Specify,

simulate and optimise systems at higher levels of abstraction– Performance– Behavior

&Create

new and reuse old IP&Efficiently traverse the path to hardware/software implementations&Use a design environment that supports your design flow

System Level Design FlowAlgorithm Product Specification Architecture

Functional Validation

Architectural Validation

Algorithmic Models

Co-Design

Architectural Models

Software

CoVerification

Hardware

Performance Modeling&Abstract performance models– Enable trade-off estimations– Examples: Modeling of power consumption, delay&Performance

models with behavioral

functionality– Scheduling of functions not fully specified– Resource bindings not fully specified

Behavioral Modeling&Untimed functional– Reactive control– Dataflow

space

&Timed functional space– Behavioral process– RTL process

The Major Challenges in System Level Design&Tight

coupling of dataflow and control&Reuse of IP at high abstraction levels&Structured methods to communicate and handle the system complexity– Software– Architecture

How real systems look ...

control

dataflow

control

control

dataflow

SystemC A Modeling Environment for Hardware and Software

SystemC A Modeling Environment for Hardware and Software&What

is SystemC?&Language overview&System simulation in SystemC&Example&What is SystemC useful for?

SystemC A C++ Class Based ApproachProcess 3

sc_signalsc_ sig naProcess 2

Process 1

sc_signed sc_logic

l

sc_sync sc_aproc

sc_async

&System

description: Multiple concurrent Processes&Communication: Signals, clocks, reset&Rich variety of hardware data types&Model at all levels of abstraction

System Simulation in SystemC&SystemC consists of– Set of header files describing the C++ classes– Link library that contains a cycle-based simulation kernel&An

ANSI C++ compliant compiler can compile SystemC, together with your program&The resulting executable serves as a simulator for the system described

Language Overview: Modules and Processes&Modules

contain other modules or processes&Processes are used to describe functionality&Communication between processes depends on signals, no global variables&Processes can be reactive to any input signal or to a clock signal

Process Types&Synchronous processes– Timing control statements like wait() implement synchronization and writing– Instructions between timing control statements are executed without delay&Asynchronous processes– I

nstructions are executed without delay– Local variables are redefined each time the block is invoked

Various Levels of Abstraction&The

more details you have to simulate, the slower is the simulation&Pure functionality of the system, algorithm&Software and testbenches can be described in C++&Hardware implementation– Behavioral, RTL style models– Handshaking, clock, reset possible

SystemC System Level

Algorithm Behavioral RTL